TCA5013 Datasheet, PDF (45/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

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TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
REGISTER
ADDRESS
0x02
0x02
0x02
0x02
0x02
0x03
0x03
0x04
0x04
0x05
0x05
0x06
0x06
0x07
0x07
0x07
0x08
0x08
DESCRIPTION
FIELD NAME
User Card Clock Settings
In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to ~1.2 MHz
0: CLKUC is set by Bit[6] or Bit[5] or Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
Bit is ignored in Sync mode
INTERN_CLK_UC
In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to 0
0: CLKUC is set by Bit[5] or Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
1: CLKUC is set to 0
0: CLKUC is set by Bit5.
CLK0_UC
In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to 1
0: CLKUC is set by Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
Usable only is CLK_ENABLE_SYNC=0
1: CLKUC is set to 1
0: CLKUC is set to 1
CLK1_UC
In asynchronous operating mode
(START_ASYNC=1)
000: CLKUC frequency = CLKIN1
001: CLKUC frequency = CLKIN1/2.
010: CLKUC frequency = CLKIN1/4.
011: CLKUC frequency = CLKIN1/5.
100: CLKUC frequency = CLKIN1/8.
101: CLKUC frequency = CLKIN1/8.
110: CLKUC frequency = CLKIN1/8.
111: CLKUC frequency = CLKIN1/8.
In synchronous operating mode
(START_SYNC=1)
Usable only is CLK_ENABLE_SYNC=1
[111:000] : CLKUC = CLKIN1
CLK_DIV_UC
Asynchronous Mode ATR EARLY Counter MSB for
User Card
MSB (8-bits) of programmable 10-bit clock counter value. EARLY_COUNT_HI_UC
Asynchronous Mode ATR EARLY Counter LSB for
User Card
LSB (2-bits) of programmable 10-bit clock counter value. EARLY_COUNT_LO_UC
Asynchronous Mode ATR MUTE Counter MSB for
User Card
MSB (8-bits) of programmable 16-Bit clock counter
value.
MUTE_COUNT_HI_UC
Asynchronous Mode ATR MUTE Counter LSB for
User Card
LSB (8-bits) of programmable 16-Bit clock counter value. MUTE_COUNT_LO_UC
User Card IO Slew Rate Settings
3 Bit value defining the rise time of IOUC
IO_TR_UC
2 Bit value defining the fall time of IOUC
IO_TF_UC
User Card Clock Slew Rate Settings
4 Bit value defining the rise time and fall time of the
CLKUC
CLK_SR_UC
BIT R/W DEFAULT
7
R/W
1'b0
6
R/W
1'b0
5
R/W
1'b0
[4:2] R/W
3'b011
[7:0] R/W 8'b10101010
[7:6] R/W
2'b00
[7:0] R/W 8'b10100100
[7:0] R/W 8'b01110100
[7:5] R/W
[4:3] R/W
3'b100
2'b00
[7:4] R/W
4'b1010
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