TCA5013 Datasheet, PDF (35/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

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TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
8.4.8 RST Operation
The RST pin operation depends on the mode in which the card interface has been activated. For user card
interface and all the SAM card interfaces, in asynchronous mode (see Asynchronous Operating Mode) the RST
pin status is automatically controlled by the TCA5013 internal state machine.
In synchronous mode (Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode) the RST
pin status is controlled by the TCA5013 internal state machine, until the activation sequence is complete. After
activation is complete, the RST pin status is controlled by RST bit (bit [3]) in the user card synchronous mode
settings register (Reg 0x09). This operation is described in further detail in Synchronous Type 1 Operating Mode
and Synchronous Type 2 Operating Mode.
8.4.8.1 Current Limiting On RST
The card RST pins have a current limiting feature that prevents excess current from being drawn on them. When
an external load tries to draw a current higher than the limit, the device responds by adjusting the V_OH or V_OL to
limit the current. The device does not deactivate the card interface when over current limit of the RST pins are
reached.
8.4.9 Interrupt Operation
The INT pin is an open drain active low output pin that needs to be pulled up to V_DDI with an external pull-up
resistor. The pull-up resistor shall be sized such that the rise time of the INT pin is < 100 µs. This is important
since slower rise time could cause POR Interrupt to not be detected by the processor during TCA5013 startup.
Generally speaking faster rise times on the INT line will reduce the chances of missing interrupts. There various
interrupt events in the TCA5013 that can cause the INT pin to be asserted low. These interrupt events are
described in the below sections.
8.4.9.1 Card Insertion And Removal
When card insertion or removal is detected on the user card interface (see User Card Insertion / Removal
Detection) the INT_UC bit (bit[7]) of interrupt status register (Reg 0x41) and the PRESL_UC bit (bit[2]) of User
card interface status register (Reg 0x00) are both set to 1 and the INT pin is asserted low. INT_UC is cleared
and the INT pin is released when the interrupt status register is read. PRESL_UC is cleared only when the user
card interface status register is read.
8.4.9.2 Over Current Fault
When the current drawn on the VCC pin of any of the card interfaces exceeds the over current limit (see
Electrical Characteristics—Fault Condition Detection) the PROT bit (bit[4]) of the card interface status register
(Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set. The interrupt
bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set and the INT pin is
asserted low. The interrupt bit is cleared and the INT pin is released, when the interrupt status register is read.
The PROT bit is cleared only when the corresponding card interface status register is read.
8.4.9.3 Supervisor Fault
When the voltage on the VDD pin falls below the V_DDTH the INT_SUPL bit (bit[2] of Reg 0x41) and The
STAT_SUPL bit (bit[1], Reg 0x10) are both set to 1 and the INT pin is asserted low. The INT_SUPL bit is cleared
and the INT pin is released when the interrupt status register is read. The STAT_SUPL bit clears when the fault
condition goes away, that is, V_DD > V_DDTH
8.4.9.4 Over Temperature Fault
When the die temperature exceeds a safe operating temperature (typ. 125°C) INT_OTP bit (bit[3], Reg 0x41) and
The STAT_OTP bit (bit[2], Reg 0x10) are both set to 1 and the INT pin is asserted low. The INT_OTP bit is
cleared and the INT pin is released when the interrupt status register is read. The STAT_OTP clears when the
fault condition goes away.
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