TCA5013 Datasheet, PDF (22/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
VCCUC
CLKUC
C4
t _S2-VCC-CLK
t _S2-CLK-C4
t _S2-CLK-HI
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All High levels refer to 0 .9 Vcc
All Low levels refer to 0 . 1 Vcc
t _R = t _F < 0 .5 μs
IOUC
INT
RSTUC
RST stays LOW through entire activation
Figure 5. Synchronous Type 2 Activation Sequence
Once synchronous type 2 activation has been initiated, the following sequence of events occur on the user card
interface:
• VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.
• V_CC is applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).
• A single pulse is applied to CLKUC per the t_S2-CLK-HI timing defined in Table 3.
• The C4 line is held low through the V_CC ramp.
• The C4 line is released high per the t_S2-CLK-C4 timing defined in Table 3.
• After C4 is released CLKUC is controlled by clock settings register (Reg 0x02).
• After V_CC is stable, the IOUC line is pulled up to V_CC.
• After V_CC is stable, C8 reflects value in bit [4] Reg 0x09.
• IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.
• INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.
• IOMC1 shall stay pulled up to V_DDI , that is, IOMC1 shall not be pulled low until INT is asserted.
• CLKIN1 shall toggle only after INT is asserted.
• RSTUC is controllable by I²C after INT is asserted.
Table 3. Synchronous Type 2 Card Activation Timing Characteristics
t_S2-VCC-CLK
t_S2-CLK-C4
t_S2-CLK-HI
MIN TYP MAX UNIT
5
20
µs
14 18
22
µs
7
9
11
µs
22
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