TCA5013 Datasheet, PDF (36/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
www.ti.com
8.4.9.5 EARLY Fault
In Asynchronous Operating Mode when the ATR response from the smartcard is received before the ‘ATR valid
window’ (see Figure 6) the EARLY bit (bit [6]) of card interface status register (Reg 0x00 for user card, Reg 0x10
for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The interrupt bit
corresponding to the card interface in the interrupt status register (Reg 0x41) is also set. The interrupt bit is
cleared and the INT pin is released, when the interrupt status register is read. The EARLY bit is cleared only
when the corresponding card interface status register is read.
8.4.9.6 MUTE Fault
In Asynchronous Operating Mode when the ATR response from the smartcard is received after the ‘ATR valid
window’ (refer to Figure 6) the MUTE bit (bit [5]) of card interface status register (Reg 0x00 for user card, Reg
0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The
interrupt bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set. The
interrupt bit is cleared and the INT pin is released, when the interrupt status register is read. The EARLY bit is
cleared only when the corresponding card interface status register is read.
8.4.9.7 Synchronous Activation Complete
In synchronous activation mode (see Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating
Mode) once the activation sequence is completed, the INT_SYNC_COMPLETE bit (bit[1]) of interrupt status
register (Reg 0x41) is set and the INT pin is asserted low. The INT_SYNC_COMPLETE bit is cleared and the
INT pin is released when the interrupt status registers is read.
8.4.9.8 V_CC Ramp Fault
During any activation sequence if the V_CC voltage fails to ramp to programmed value within 5 ms (typ), then the
VCC_FAIL bit (bit[0]) of card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for
SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The interrupt bit corresponding to the card
interface in the interrupt status register (Reg 0x41) is also set. The interrupt bit is cleared and the INT pin is
released, when the interrupt status register is read. The VCC_FAIL bit is cleared only when the corresponding
card interface status register is read.
8.4.9.9 GPIO Input State Transition
When there is a state change on a GPIO pin configured as an input the INT_GPIO bit (bit[0]) of the interrupt
status register (Reg 0x41) is set and the INT pin is asserted low. The INT_GPIO bit is cleared and the INT pin is
released when the interrupt status register is read.
8.4.9.10 POR Interrupt
Whenever the device comes out of Power Off Mode or Shutdown Mode it goes through a power-on-reset (POR).
Once the device internal power up sequence is completed the INT pin is asserted low without any of the bits in
the interrupt status register (Reg 0x41) being set. Once the interrupt status register is read, the INT pin is
released. When the device is coming out of shutdown mode of power off mode, none of the device functions will
be available until the POR interrupt is asserted.
8.4.10 Power Management
The TCA5013 has power management features that enable the device to generate the appropriate card
activation voltages and monitor the device power supplies for safe and secure system operation.
8.4.10.1 Voltage Supervisor
The TCA5013 has internal voltage supervisors that monitor V_DD and V_DDI voltages. When V_DD falls below V_DDTH
all card interfaces are deactivated and the supervisor fault (see Supervisor Fault) is asserted.
The V_DDI supervisor monitors the voltage on the V_DDI pin. When V_DDI falls below V_DDITH all card interfaces are
deactivated and the device enters power off mode (see Power Off Mode). When V_DDI falls below V_DDITH the
supervisor fault is not asserted.
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