DS90UB921-Q1 Datasheet, PDF (49/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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DS90UB921-Q1
SNLS488 – MARCH 2016
Figure 35 and Figure 36 PCB layout examples are derived from the layout design of the DS90UB921-Q1EVM
Evaluation Board. The graphic and layout description are used to determine proper routing when designing the
Serializer board. Figure 35 shows the high speed FPD-Link III traces routed differentially to the connector. The
traces are buried in an internal layer with a GND layer and power layer on each adjacent layer. Burying the
traces helps reduce emissions, and it is important not to route other high speed signals near these critical signal
traces. 100Ω differential characteristic impedance and 50Ω single-ended characteristic impedance traces are
maintained as much as possible for both STP and coax applications. For layout of a coax board, 100Ω coupled
traces should be used with the DOUT- termination near to the connector.
Buried signal traces
Figure 35. DS90UB921-Q1 Serializer Example Layout, Inner Layer
Figure 36 shows the high speed FPD-Link III traces close to the DOUT± pins. In this case, the AC coupling
capacitors are on the opposide side of the board, so there is an additional via that would not be needed if the
components were all on the same side. This via, the AC coupling capacitors, the common-mode choke, and the
second via (going to the buried traces to the connector) are all place closely together so that the impedance
discontinuity appears as tightly grouped as possible.
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