DS90UB921-Q1 Datasheet, PDF (13/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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DS90UB921-Q1
SNLS488 – MARCH 2016
SDA
t_f
SCL
START
t_LOW
t_r
t_f
t_HD;STA
t_SP
t_r
t_BUF
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
t_SU;STO
REPEATED
START
STOP START
Figure 10. Serial Control Bus Timing Diagram
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_LHT
CML Output Low-to-High
Transition Time
t_HLT
CML Output High-to-Low
Transition Time
See Figure 5
t_DIS
Data Input Setup to PCLK
See Figure 6
t_DIH
Data Input Hold from PCLK
t_PLD
Serializer PLL Lock Time
See Figure 7 ⁽¹⁾
t_SD
Delay — Latency
See Figure 8
Output Total Intrinsic Jitter, Jitter R_L = 100Ω
t_TJIT
frequency > f/10
Bit Error Rate ≥10^{-10 (2) (3)}
f = 96MHz
See Figure 9
PIN/FREQ.
DOUT+,
DOUT-
R[7:0],
G[7:0],
B[7:0], HS,
VS, DE,
PCLK
f=5-
96MHz
f=5-
96MHz
DOUT+,
DOUT-
MIN TYP
80
80
2.0
2.0
MAX UNIT
ps
ps
ns
ns
131*T
145*T
0.25
ns
ns
0.30 UI
(1) tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by characterization and is not tested in production.
(3) UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.
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