DS90UB921-Q1 Datasheet, PDF (38/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB921-Q1
SNLS488 – MARCH 2016
ADD
(dec)
101
ADD
(hex)
0x65
REGISTER NAME
Pattern Generator
Configuration
102
0x66 Pattern Generator
Indirect Address
103
0x67 Pattern Generator
Indirect Data
198
0xC6 ICR
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Table 7. Serial Control Bus Registers (continued)
BIT(S)
7:5
4
TYPE
RW
3
RW
2
RW
1
RW
0
RW
7:0
RW
7:0
RW
7:6
5
RW
4:1
0
RW
DEFAULT
(hex)
0x00
0x00
0x00
FUNCTION
DESCRIPTION
Pattern
Generator 18
Bits
Pattern
Generator
External Clock
Pattern
Generator
Timing Select
Pattern
Generator Color
Invert
Pattern
Generator Auto-
Scroll Enable
Indirect Address
Indirect Data
IS_RX_INT
INT Enable
Reserved
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels
of brightness and the R, G, and B outputs use the six most significant color
bits.
0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of
brightness.
Select External Clock Source
1: Selects the external pixel clock when using internal timing.
0: Selects the internal divided clock when using internal timing
This bit has no effect in external timing mode (PATGEN_TSEL = 0).
Timing Select Control
1: The Pattern Generator creates its own video timing as configured in the
Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync
Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and
Sync Configuration registers.
0: the Pattern Generator uses external video timing from the pixel clock,
Data Enable, Horizontal Sync, and Vertical Sync signals.
Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the next enabled
pattern after the number of frames specified in the Pattern Generator Frame
Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
This 8-bit field sets the indirect address for accesses to indirectly-mapped
registers. It should be written prior to reading or writing the Pattern
Generator Indirect Data register.
See AN-2198 (SNLA132).
When writing to indirect registers, this register contains the data to be
written. When reading from indirect registers, this register contains the read
back value.
See AN-2198 (SNLA132)
Reserved
Interrupt on Receiver interrupt
Enables interrupt on indication from the Receiver. Allows propagation of
interrupts from downstream devices
Reserved
Global Interrupt Enable
Enables interrupt on the interrupt signal to the controller.
38
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