DS90UB921-Q1 Datasheet, PDF (4/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB921-Q1
SNLS488 – MARCH 2016
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Pin Functions (continued)
NAME
PIN
NUMBER
I/O, TYPE
DESCRIPTION
HS
3
I, LVCMOS, Horizontal Sync Input Pin
PD
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when
the Control Signal Filter is enabled. There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions
per 130 PCLKs.
See Video Control Signal Filter.
VS
4
I, LVCMOS, Vertical Sync Input Pin
PD
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
width is 130 PCLKs.
See Video Control Signal Filter.
DE
5
I, LVCMOS, Data Enable Input Pin
PD
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when
the Control Signal Filter is enabled. There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions
per 130 PCLKs.
See Video Control Signal Filter.
PCLK
10
I, LVCMOS, Pixel Clock Input Pin. Strobe edge set by TRFB configuration register. See Table 7
PD
0x03[0].
I2S_CLK,
I2S_WC,
I2S_DA
13, 12, 11
Multi-function
pin
I, LVCMOS,
PD
Digital Audio Interface Data Input Pins
Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
OPTIONAL PARALLEL INTERFACE - Layout note: for unused interface pins, tie to an external pulldown
GPIO[3:0]
36, 35, 26, 25
Multi-function
pin
I/O, LVCMOS,
PD
General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin
or configuration register. See Table 7 0x0D - 0x0F.
Leave open if unused.
Shared with DIN9, DIN8, DIN1 and DIN0
GPO_REG[
7:4]
12, 11, 44, 43
Multi-function
pin
O, LVCMOS,
PD
General Purpose Outputs and set by configuration register. See Table 7 0x0F - 0x11.
Share with I2S_WC, I2S_DA, or DIN17, DIN16.
CONTROL
PDB
21
I, LVCMOS, Power-down Mode Input Pin
PD
PDB = H, device is enabled (normal operation)
Refer to Power Up Requirements and PDB Pin section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the
PLL is shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL
24
S
Device Configuration Select. See Table 5.
FSEL
I²C
IDx
SCL
SDA
15
I, LVCMOS, Frequency Mode Select. Enables Intermediate Frequency mode for coaxial operation.
PU
See Frequency Mode Optimizations.
6
S
I²C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See
Table 6.
8
I/O, Open I²C Clock Input / Output Interface
Drain
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
9
I/O, Open I²C Data Input / Output Interface
Drain
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
4
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