DS90UB921-Q1 Datasheet, PDF (43/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

www.ti.com
Typical Application (continued)
HOST
Graphics
Processor
V_DDIO V_DD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
I2S AUDIO ³
(STEREO)
DOUT+
DOUT-
DS90UB921-Q1
Serializer
SCL
SDA
IDx
DAP
DS90UB921-Q1
SNLS488 – MARCH 2016
FPD-Link III
1 Pair / AC Coupled
MODE_SEL
INTB
PDB
OSS_SEL
OEN
MODE_SEL
INTB_IN
SCL
SDA
IDx
V_DD33 V_DDIO
(3.3V) (1.8V or 3.3V)
RIN+
RIN-
DS90UB926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
RGB Display
720p
24-bit color depth
3 _{I2S AUDIO}
(STEREO)
MCLK
DAP
HOST
Graphics
Processor
Figure 28. Typical STP System Diagram
V_DDIO V_DD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
I2S AUDIO ³
(STEREO)
DOUT+
DOUT-
DS90UB921-Q1
Serializer
SCL
SDA
IDx
DAP
FPD-Link III
1 Pair / AC Coupled
V_DDIO V_DD33 V_DD12
(1.8V or 3.3V) (3.3V) (1.2V)
FPD-Link
(Open LDI)
CLK1+/-
RIN0+
RIN0-
D0+/-
D1+/-
D2+/-
PDB
MODE_SEL
INTB_IN
INTB MODE_SEL[1:0]
SCL
SDA
IDx
DS90UB948-Q1
Deserializer
D3+/-
CLK2+/-
D4+/-
D5+/-
D6+/-
D7+/-
LVDS
Display
720p60
or Graphic
Processor
Figure 29. Typical Coax Applications Diagram
8.3.1 Design Requirements
For the typical design application, use the following as input parameters.
Table 8. Design Parameters
DESIGN PARAMETER
VDDIO
VDD33
AC Coupling Capacitor for DOUT±
PCLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
100 nF on DOUT+ and 100nF on DOUT- for STP
330nF on DOUT+ and 150nF on DOUT- for Coax
74.25 MHz
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
Submit Documentation Feedback
43