DS90UB921-Q1 Datasheet, PDF (44/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
8.3.2 Detailed Design Procedure
Figure 26 shows a typical application of the DS90UB921-Q1 serializer for an 96 MHz 24-bit Color Display
Application. The CML outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines
for STP applications and 0.33 μF / 0.15 μF AC coupling capacitors for coax applications. The same AC coupling
capacitor values should be used on the paired deserializer board. The serializer has an internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors and two (2)
additional 1μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2)
VDDs (VDD33 and VDDIO) for effective noise suppression. The interface to the graphics source is with 3.3V
LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.
8.3.3 Application Curves
Time (200 ps/DIV)
Figure 30. Serializer Eye Diagram with 74.25 MHz TX Pixel
Clock
Time (2.0 ns/DIV)
Figure 31. Serializer CML Output with 74.25 MHz TX Pixel
Clock
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