DS90UB921-Q1 Datasheet, PDF (46/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Power Up Requirements and PDB Pin (continued)
Symbol
t₁
t₄
Table 9. Power-Up Sequencing Constraints (continued)
Description
VDD33 delay time
Startup time
Test Conditions
Min
Typ
V_IL of rising edge (VDDIO) to V_IL of rising
edge (VDD33)
The power supplies may be ramped
>0
simultaneously. If sequenced, VDDIO
should be first..
The part is powered up after the startup
time has elapsed from the moment PDB
goes HIGH. Local I2C is available to
read/write 921 registers after this time.
Max
Units
ms
<1
ms
This device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separate
power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal
description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs.
In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.
9.2 CML Interconnect Guidelines
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– – S = space between the pair
– – 2S = space between pairs
– – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: www.ti.com/lvds.
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