DS90UB921-Q1 Datasheet, PDF (16/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB921-Q1
SNLS488 – MARCH 2016
Feature Description (continued)
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Figure 13. FPD-Link III Serial Stream
The device supports clocks in the range of 5 MHz to 96 MHz. The actual line rate is 3.36 Gbps maximum and
525 Mbps Minimum.
7.3.2 Low Speed Back Channel Data Transfer
The Low-Speed Backward Channel (LS_BC) of the DS90UB921-Q1 provides bidirectional communication
between the display and host processor. The information is carried back from the Deserializer to the Serializer
per serial symbol. The back channel control data is transferred over the single serial link along with the high-
speed forward data, DC balance coding and embedded clock information. This architecture provides a backward
path across the serial link together with a high speed forward channel. The back channel contains the I²C, CRC
and 4 bits of standard GPIO information with 3.1 Mbps line rate in Coax mode and low frequency STP mode,
and 4.4Mbps line rate in high frequency STP mode. The back channel data rate is configured automatically when
STP or Coax is selected (see Frequency Mode Optimizations).
7.3.3 Common Mode Filter Pin (CMF)
The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin
for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.
7.3.4 Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 14.
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