DS90UB921-Q1 Datasheet, PDF (22/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB921-Q1
SNLS488 – MARCH 2016
SAMPLE RATE (kHz)
192
32
44.1
48
96
192
Table 4. Audio Interface Frequencies (continued)
I2S DATA WORD SIZE (BITS)
24
32
32
32
32
32
I2S CLK (MHz)
9.216
2.048
2.822
3.072
6.144
12.288
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7.3.17 Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics.
7.3.17.1 BIST Configuration and Status
The BIST mode is enabled at the deseralizer by the Pin select (BISTEN and BISTC) or configuration register
(Table 7) through the deserializer. When LFMODE = 0, the pin based configuration defaults to external PCLK or
33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC
frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the pin based configuration
defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to
35 bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 7.
7.3.17.1.1 Sample BIST Sequence
See Figure 16 for the BIST mode flow diagram.
Step 1: BIST Mode is enabled via the BISTEN pin of the deserializer. The desired clock source is selected
through BISTC pin.
Step 2: The DS90UB921-Q1 serializer is woken up through the back channel if it is not already on. The all zero
pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the
deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and
BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low
for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to
determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there
was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST
is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 17 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
reducing signal condition enhancements (Rx Equalization).
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