DS90UB921-Q1 Datasheet, PDF (45/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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9 Power Supply Recommendations
DS90UB921-Q1
SNLS488 – MARCH 2016
9.1 Power Up Requirements and PDB Pin
When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before
the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs
(VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not
controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs
have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or
VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.
A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.
All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.
t₀
VDDIO
GND
t₃
VDD33
GND
t₁
PDB^(*)
GND
V_{PDB_HIGH}
V_{PDB_LOW}
VDD33
t₄
(*) _{It is recommended to assert PDB (active High) with a microcontroller rather than an RC filter}
network to help ensure proper sequencing of PDB pin after settling of power supplies.
Figure 32. Timing Diagram of DS90UB921-Q1
Table 9. Power-Up Sequencing Constraints
Symbol
Description
Test Conditions
Min
Typ
Max
Units
VDDIO
VDDIO voltage range
3.0
3.6
V
1.71
1.89
V
VDD33
VDD33 voltage range
3.0
3.6
V
PDB LOW threshold
V_{PDB_LOW}
Note: V_PDB should not exceed
limit for respective I/O voltage
VDDIO = 3.3V ± 10%
0.8
V
before 90% voltage of VDD12
V_{PDB_HIGH}
t₀
PDB HIGH threshold
VDDIO rise time
VDDIO = 3.3V ± 10%
These time constants are specified for
rise time of power supply voltage ramp 0.05
(10% - 90%)
2.0
V
<1.5
ms
These time constants are specified for
t₃
VDD33 rise time
rise time of power supply voltage ramp 0.05
<1.5
ms
(10% - 90%)
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