DS90UB921-Q1 Datasheet, PDF (29/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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ADD
(dec)
0
1
ADD
(hex)
0x00
REGISTER NAME
I2C Device ID
BIT(S)
7:1
0
0x01 Reset
7
6:2
1
0
3
0x03 Configuration [0]
7
6
5
4
3
2
1
0
DS90UB921-Q1
SNLS488 – MARCH 2016
Table 7. Serial Control Bus Registers
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DEFAULT
(hex)
0x00
0xD2
FUNCTION
DESCRIPTION
Device ID
ID Setting
Soft Sleep
Digital RESET1
Digital RESET0
Back channel
CRC Checker
Enable
I2C Remote
Write Auto
Acknowledge
Filter Enable
I2C Pass-
through
PCLK Auto
TRFB
7–bit address of Serializer
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
1: Enable power down when no Bidirectional Control Channel Link detected.
0: Do not power down when no Bidirectional Control Channel Link detected.
Reserved
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
Back Channel Check Enable
1: Enable
0: Disable
Reserved
Automatically Acknowledge I2C Remote Write When enabled, I2C writes to
the Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are
immediately acknowledged without waiting for the Deserializer to
acknowledge the write. This allows higher throughput on the I2C bus
1: Enable
0: Disable
HS, VS, DE two clock filter When enabled, pulses less than two full PCLK
cycles on the DE, HS, and VS inputs will be rejected
1: Filtering enable
0: Filtering disable
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
Reserved
Switch over to internal OSC in the absence of PCLK
1: Enable auto-switch
0: Disable auto-switch
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock Edge.
0: Parallel Interface Data is strobed on the Falling Clock Edge.
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
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