DS90UB921-Q1 Datasheet, PDF (36/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB921-Q1
SNLS488 – MARCH 2016
ADD
(dec)
20
ADD
(hex)
0x14
REGISTER NAME
Oscillator Clock
Source and BIST
Status
22
0x16 BCC Watchdog
Control
23
0x17 I2C Control
24
0x18 SCL High Time
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Table 7. Serial Control Bus Registers (continued)
BIT(S)
7:3
2:1
TYPE
RW
0
R
7:1
RW
0
RW
7
RW
6
5:4
RW
3:0
RW
7:0
RW
DEFAULT
(hex)
0x00
0xFE
0x5E
0xA1
FUNCTION
DESCRIPTION
OSC Clock
Source
BIST Enable
Status
Timer Value
Timer Control
I2C Pass All
SDA Hold Time
I2C Filter Depth
SCL HIGH Time
Reserved
OSC Clock Source
(When LFMODE = 1, Oscillator = 12.5MHz ONLY)
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
BIST status
1: Enabled
0: Disabled
The watchdog timer allows termination of a control channel transaction if it
fails to complete within a programmed amount of time.
This field sets the Bidirectional Control Channel Watchdog Timeout value in
units of 2 ms.
This field should not be set to 0
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
I2C Control
1: Enable Forward Control Channel pass-through of all I2C accesses to I2C
Slave IDs that do not match the Serializer I2C Slave ID.
0: Enable Forward Control Channel pass-through only of I2C accesses to
I2C Slave IDs matching either the remote Deserializer Slave ID or the
remote Slave ID.
Reserved
Internal SDA Hold Time
Configures the amount of internal hold time provided for the SDA input
relative to the SCL input. Units are 40 ns
Configures the maximum width of glitch pulses on the SCL and SDA inputs
that will be rejected. Units are 5 ns
I2C Master SCL High Time
This field configures the high pulse width of the SCL output when the
Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal
oscillator clock frequency. The default value is set to provide a minimum
5us SCL high time with the internal oscillator clock running at 32.5MHz
rather than the nominal 25MHz.
36
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