DS90UB921-Q1 Datasheet, PDF (19/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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DS90UB921-Q1
SNLS488 – MARCH 2016
Feature Description (continued)
7.3.10 Serial Link Fault Detect
The serial link fault detection is able to detect any of following seven (7) conditions:
1. cable open
2. “+” to “-“ short
3. “+” short to GND
4. “-“ short to GND
5. “+” short to battery
6. “-“ short to battery
7. Cable is linked correctly
If any one of the fault conditions (first 6 conditions above) occurs, The Link Detect Status is 0 (cable is not
detected) on bit 0 of address 0x0C Table 7.
7.3.11 Pixel Clock Edge Select (TRFB)
The TRFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines
the edge that the data is latched on. If TRFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If
TRFB is LOW (‘0’), data is latched on the Falling edge of the PCLK.
7.3.12 Frequency Mode Optimizations
HFMODE, LFMODE, and IFMODE are set through a combination of the FSEL pin and MODE_SEL pin, with
register overrides for both. These pins (or register overrides) will configure the DS90UB921-Q1 into either Low
Frequency Mode (LFMODE), Intermediate Frequency mode (IFMODE), or High Frequency mode (HFMODE).
See Table 1 for details on how each mode is enabled.
FSEL (pin 15, or
register 0x35[7:6])
L
H
H
L
Table 1. HFMODE / LFMODE / IFMODE Configuration Table
ALTERNATE
FREQUENCY (set by
MODE_SEL pin, or
register 0x04[1:0])
L
L
H
H
MODE
HFMODE
HFMODE
IFMODE
LFMODE
PCLK RANGE for COAX PCLK RANGE for STP
N/A
48 - 96 MHz
24 - 48 MHz
15 - 24 MHz
15 - 96 MHz
N/A
N/A
5 - 15 MHz
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