DS90UB921-Q1 Datasheet, PDF (15/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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7 Detailed Description
DS90UB921-Q1
SNLS488 – MARCH 2016
7.1 Overview
The DS90UB921-Q1 serializer transmits a 35-bit symbol over a single serial FPD-Link III channel operating up to
3.36 Gbps line rate. The serial stream contains an embedded clock, video control signals and DC-balanced video
data and audio data which enhance signal quality to support AC coupling. The serializer is intended for use with
the DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB948-Q1, or DS90UB940-Q1 deserializers.
The DS90UB921-Q1 serializer and compatible deserializer incorporate an I²C compatible interface. The I²C
compatible interface allows programming of serializer or deserializer devices from a local host controller. In
addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between
serializer/deserializer as well as remote I²C slave devices.
The bidirectional control channel is implemented via embedded signaling in the high-speed forward channel
(serializer to deserializer) as well as lower speed signaling in the reverse channel (deserializer to serializer).
Through this interface, the BCC provides a mechanism to bridge I²C transactions across the serial link from one
I²C bus to another. The implementation allows for arbitration with other I²C compatible masters at either side of
the serial link.
There are two operating modes available on DS90UB921-Q1, display mode and camera mode. In display mode,
I²C transactions originate from the host controller attached to the serializer and target either the deserializer or an
I²C slave attached to the deserializer. Transactions are detected by the I²C slave in the serializer and forwarded
to the I²C master in the deserializer. Similarly, in camera mode, I²C transactions originate from a controller
attached to the deserializer and target either the serializer or an I²C slave attached to the serializer. Transactions
are detected by the I²C slave in the deserializer and forwarded to the I²C master in the serializer.
7.2 Functional Block Diagram
24
DIN [23:0]
HS
VS
DE
PCLK
I2S_CLK ₃
I2S_WC
I2S_DA
PDB
MODE_SEL
INTB
REM_INTB
SDA
SCL
IDx
REGULATOR
D
PLL
Timing
and
Control
CMF
D_OUT +
D_OUT -
DS90UB921-Q1
Serializer
7.3 Feature Description
7.3.1 High Speed Forward Channel Data Transfer
The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or
YUV data, sync signals, I²C, and I2S audio transmitted from Serializer to Deserializer. Figure 13 illustrates the
serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link.
Data is randomized, balanced and scrambled.
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