DS90UB921-Q1 Datasheet, PDF (21/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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DS90UB921-Q1
SNLS488 – MARCH 2016
Note: GPO_REG4 of the DS90UB921-Q1 can be used as a forward channel GPIO, outputting on GPIO0 of
DS90UB928Q-Q1. This is configured as follows:
• Set DS90UB921-Q1 in 18-bit mode by register 0x12[2] = 1.
• Set DS90UB928Q-Q1 register 0x1D[0] = 1 and 0x1D[2] = 1; this enables GPIO0 of DS90UB928Q-Q1 as an
output.
• Set DS90UB921-Q1 register 0x0F[4] = 1 and 0x0F[5] = 1; this enables GPO_REG4 of DS90UB921-Q1 as an
input.
Similarly GPO_REG5 of DS90UB921-Q1 can output to GPIO1 of DS90UB928Q-Q1:
• Set DS90UB921-Q1 in 18-bit mode by register 0x12[2] = 1.
• Set DS90UB928Q-Q1 register 0x1E[0] = 1 and 0x1E[2] = 1; this enables GPIO1 of DS90UB928Q-Q1 as an
output.
• Set DS90UB921-Q1 register 0x10[0] = 1 and 0x10[1] = 1; this enables GPO_REG5 DS90UB921-Q1 as an
input.
7.3.15.2 GPO_REG[7:4] Enable Sequence
GPO_REG[7:4] are the outputs only pins. They must be programmed through the local register bits. See Table 3
for the GPO_REG enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 7 on DS90UB921-Q1 only. The
deserializer is automatically configured as in the 18-bit mode.
Step 2: To enable GPO_REG7 outputs an “1”, write 0x09 to address 0x11 on DS90UB921-Q1.
#
DESCRIPTION
1
Enable 18-bit mode
2
GPO_REG7
3
GPO_REG6
4
GPO_REG5
5
GPO_REG4
Table 3. GPO_REG Enable Sequencing Table
DEVICE
DS90UB921-Q1
DS90UB921-Q1
DS90UB921-Q1
DS90UB921-Q1
DS90UB921-Q1
LOCAL ACCESS
0x12 = 0x04
0x11 = 0x09
0x11 = 0x01
0x10 = 0x90
0x10 = 0x10
0x10 = 0x09
0x10 = 0x01
0x0F = 0x90
0x0F = 0x10
LOCAL OUTPUT
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
7.3.16 I2S Transmitting
In normal 24-bit RGB operation mode, the DS90UB921-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC
and I2S_DA. The optionally packetized audio information can be transmitted during the video blanking (data
island transport) or during active video (forward channel frame transport). Note: The bit rates of any I2S bits must
maintain one fourth of the PCLK rate. Table 4 covers the range of I2S sample rates.
SAMPLE RATE (kHz)
32
44.1
48
96
192
32
44.1
48
96
Table 4. Audio Interface Frequencies
I2S DATA WORD SIZE (BITS)
16
16
16
16
16
24
24
24
24
I2S CLK (MHz)
1.024
1.411
1.536
3.072
6.144
1.536
2.117
2.304
4.608
Copyright © 2016, Texas Instruments Incorporated
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