DS90UB921-Q1 Datasheet, PDF (20/57 Pages) Texas Instruments – 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
7.3.13 Interrupt Pins – Funtional Description and Usage (INTB, REM_INTB)
The REM_INTB pin mirrors the status of INTB_IN from the remote deserializer. Any change in INTB_IN status of
the remote device will be reflected at the REM_INTB output of the serializer. REM_INTB will remain LOW until
lock is achieved with the downstream deserializer. Alternately, the INTB pin can be set to trigger on remote
interrupts by following the steps below.
1. On DS90UB921-Q1, read register 0xC7.
2. On DS90UB921-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1
3. Deserializer INTB_IN is set LOW by some downstream device.
4. DS90UB921-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt
condition.
5. External controller detects INTB = LOW; to determine interrupt source, read ISR register 0xC7.
6. A read to ISR will clear the interrupt at the DS90UB921-Q1, releasing INTB.
7. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN on the deserializer. The system is now ready to return to step (1) at next falling edge of INTB_IN.
If using the REM_INTB pin instead of INTB for remote interrupts, the IS_RX_INT bit (0xC6[5]) of the serializer's
ICR register must be set low (default) masking remote interrupts to the INTB pin.
7.3.14 Internal Pattern Generation
The DS90UB921-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and
repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down
mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test
pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application
Note AN-2198 (SNLA132).
7.3.15 GPIO[3:0] and GPO_REG[7:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB921-Q1 can be used as the general
purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) applications.
7.3.15.1 GPIO[3:0] Enable Sequence
See Table 2 for the GPIO enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 7 on DS90UB921-Q1 only. The
deserializer is automatically configured as in the 18-bit mode.
Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB921-Q1, then write 0x05 to
address 0x1F on the deserializer.
#
DESCRIPTION
1
Enable 18-bit
mode
2
GPIO3
3
GPIO2
4
GPIO1
5
GPIO0
Table 2. GPIO Enable Sequencing Table
DEVICE
DS90UB921-Q1
DS90UB926Q-Q1
DS90UB921-Q1
DS90UB926Q-Q1
DS90UB921-Q1
DS90UB926Q-Q1
DS90UB921-Q1
DS90UB926Q-Q1
DS90UB921-Q1
DS90UB926Q-Q1
FORWARD CHANNEL
0x12 = 0x04
Auto Load from DS90UB921-Q1
0x0F = 0x03
0x1F = 0x05
0x0E = 0x30
0x1E = 0x50
0x0E = 0x03
0x1E = 0x05
0x0D = 0x93
0x1D = 0x95
BACK CHANNEL
0x12 = 0x04
Auto Load from DS90UB921-Q1
0x0F = 0x05
0x1F = 0x03
0x0E = 0x50
0x1E = 0x30
0x0E = 0x05
0x1E = 0x03
0x0D = 0x95
0x1D = 0x93
20
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