LM3S6952 Datasheet, PDF (94/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller

System Control
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set, allowing the
extended capabilities of the RCC2 register to be used while also providing a means to be
backward-compatible to previous parts. The fields within the RCC2 register occupy the same bit
positions as they do within the RCC register as LSB-justified.
The SYSDIV2 field is 2 bits wider than the SYSDIV field in the RCC register so that additional larger
divisors are possible, allowing a lower system clock frequency for improved Deep Sleep power
consumption. The PLL VCO frequency is 400 MHz.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2810
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
USERCC2
reserved
SYSDIV2
reserved
Type R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PWRDN2 reserved BYPASS2
reserved
OSCSRC2
reserved
Type RO
RO
R/W
RO
R/W
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
Reset
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
Bit/Field
31
30:29
28:23
22:14
13
12
Name
USERCC2
reserved
SYSDIV2
reserved
PWRDN2
reserved
Type
R/W
RO
R/W
RO
R/W
RO
Reset
0
0
0x0F
0
1
0
Description
Use RCC2
When set, overrides the RCC register fields.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
Although the PLL VCO frequency is 400 MHz, it is predivided by 2 before
the divisor is applied.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power-Down PLL
When set, powers down the PLL.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
94
April 05, 2010
Texas Instruments-Production Data