LM3S6952 Datasheet, PDF (22/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller

Revision History
Table 1. Revision History (continued)
Date
Revision Description
■ The "Differential Sampling Range" figures in the ADC chapter were clarified.
■ The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected:
– The LQFP pin diagrams and pin tables were missing the comparator positive and negative input
pins.
– The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.
■ Additional minor data sheet clarifications and corrections.
May 2008
2972
■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously
indicated as available and have now been changed to a No Connect (NC):
– Ball C1: Changed PE7 to NC
– Ball C2: Changed PE6 to NC
– Ball D2: Changed PE5 to NC
■ As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported:
TX Activity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit
fields in the MR23 register are now marked as reserved.
■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
■ As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS.
A 12.4-kΩ resistor should be connected between ERBIAS and ground to accommodate future device
revisions (see “Functional Description” on page 434).
■ Additional minor data sheet clarifications and corrections.
July 2008
3108
■ Corrected resistor value in ERBIAS signal description.
■ Additional minor data sheet clarifications and corrections.
August 2008
3447
■ Added note on clearing interrupts to Interrupts chapter.
■ Added Power Architecture diagram to System Control chapter.
■ Additional minor data sheet clarifications and corrections.
October 2008
4149
■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ In the Ethernet chapter, major improvements were made including a rewrite of the conceptual
information and the addition of new figures to clarify how to use the Ethernet Controller interface.
■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
November 2008
4283
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
22
April 05, 2010
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