LM3S6952 Datasheet, PDF (434/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller

Ethernet Controller
Figure 16-1. Ethernet Controller
ARM Cortex M3
EMtehdeiranet ConPtrhoyllseircal
Access Layer Entity
Controller
MAC
(Layer 2)
PHY
(Layer 1)
Magnetics
RJ45
Figure 16-2 on page 434 shows more detail of the internal structure of the Ethernet Controller and
how the register set relates to various functions.
Figure 16-2. Ethernet Controller Block Diagram
Interrupt
Interrupt
Control
MACRIS
MACIACK
MACIM
Individual
Address
MACIA0
MACIA1
Receive
Control
MACRCTL
MACNP
Data
Access
MACDDATA
Transmit
Control
MACTCTL
MACTHR
MACTR
MII
Control
MACMCTL
MACMDV
MACMTXD
MACMRXD
Transmit
FIFO
Receive
FIFO
Transmit
Encoding
Pulse
Shaping
Collision
Detect
Carrier
Sense
Receive
Decoding
Clock
Recovery
TXOP
TXON
MDIX
RXIP
RXIN
Media Independent Interface
Management Register Set
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR16
MR17
MR18
MR19
MR23
MR24
Auto
Negotiation
Clock
Reference
XTALPPHY
XTALNPHY
LED0
LED1
16.2
16.2.1
Functional Description
Note: A 12.4-kΩ resistor should be connected between the ERBIAS and ground. The 12.4-kΩ
resistor should have a 1% tolerance and should be located in close proximity to the ERBIAS
pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used.
The functional description of the Ethernet Controller is discussed in the following sections.
MAC Operation
The following sections decribe the operation of the MAC unit, including an overview of the Ethernet
frame format, the MAC layer FIFOs, Ethernet transmission and reception options, and LED indicators.
434
April 05, 2010
Texas Instruments-Production Data