LM3S6952 Datasheet, PDF (18/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller

Table of Contents
Synchronous Serial Interface (SSI) ............................................................................................ 360
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 372
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 374
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 376
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 377
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 379
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 380
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 382
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 383
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 384
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 385
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 386
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 387
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 388
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 389
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 390
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 391
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 392
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 393
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 394
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 395
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 396
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 397
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 412
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 413
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 417
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 418
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 419
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 420
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 421
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 422
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 423
Register 10: I²C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 425
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 426
Register 12: I²C Slave Data (I2CSDR), offset 0x008 ........................................................................... 428
Register 13: I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 429
Register 14: I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 430
Register 15: I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 431
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 432
Ethernet Controller ...................................................................................................................... 433
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 444
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 447
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 448
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 449
Register 5: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 450
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 452
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 453
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April 05, 2010
Texas Instruments-Production Data