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LM3S6952 Datasheet, PDF (30/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller | |||
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Architectural Overview
â 1.25 DMIPS/MHz
â JTAG
â IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
â Four-bit Instruction Register (IR) chain for storing JTAG instructions
â IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
â ARM additional instructions: APACC, DPACC and ABORT
â Integrated ARM Serial Wire Debug (SWD)
â Hibernation
â System power control using discrete external regulator
â Dedicated pin for waking from an external signal
â Low-battery detection, signaling, and interrupt generation
â 32-bit real-time counter (RTC)
â Two 32-bit RTC match registers for timed wake-up and interrupt generation
â Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
â RTC predivider trim for making fine adjustments to the clock rate
â 64 32-bit words of non-volatile memory
â Programmable interrupts for RTC match, external wake, and low battery events
â Internal Memory
â 256 KB single-cycle flash
⢠User-managed flash block protection on a 2-KB block basis
⢠User-managed flash data programming
⢠User-defined and managed flash-protection block
â 64 KB single-cycle SRAM
â GPIOs
â 6-43 GPIOs, depending on configuration
â 5-V-tolerant input/outputs
â Programmable control for GPIO interrupts
⢠Interrupt generation masking
⢠Edge-triggered on rising, falling, or both
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April 05, 2010
Texas Instruments-Production Data
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