LM3S6952 Datasheet, PDF (47/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller

Stellaris® LM3S6952 Microcontroller
2.1
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
Block Diagram
Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
Interrupts
Sleep
Debug
CM3 Core
Instructions Data
Memory
Protection
Unit
ARM
Cortex-M3
Serial
Wire
Output
Trace
Trace ^Port
Port ^(SWO)
Interface
Unit
Serial Wire JTAG
Debug Port
Flash
Patch and
Breakpoint
Private Peripheral
Bus
(internal)
Adv. High-
Perf. Bus
Access Port
Data Instrumentation
Watchpoint Trace Macrocell
and Trace
Private
Peripheral
Bus
(external)
ROM
Table
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
2.2
2.2.1
Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris^® implementation.
Texas Instruments has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 47.
As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components
are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the
Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
Serial Wire and JTAG Debug
Texas Instruments has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual
for details on SWJ-DP.
April 05, 2010
47
Texas Instruments-Production Data