LM3S6952 Datasheet, PDF (15/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller

Stellaris® LM3S6952 Microcontroller
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Register 18:
Flash Memory Control (FMC), offset 0x008 ..................................................................... 162
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 164
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 165
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 166
USec Reload (USECRL), offset 0x140 ............................................................................ 168
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 169
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 170
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 171
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 172
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 173
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 174
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 175
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 176
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 177
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 178
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 179
General-Purpose Input/Outputs (GPIOs) ................................................................................... 180
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 188
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 189
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 190
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 191
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 192
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 193
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 194
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 195
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 196
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 197
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 199
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 200
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 201
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 202
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 203
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 204
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 205
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 206
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 207
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 208
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 210
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 211
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 212
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 213
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 214
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 215
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 216
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 217
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 218
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 219
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 220
April 05, 2010
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