LM3S6952 Datasheet, PDF (564/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller

Signal Tables
Table 21-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
C7
VDDA
-
Power The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
C8
GNDPHY
-
Power GND of the Ethernet PHY.
C9
GNDPHY
-
Power GND of the Ethernet PHY.
C10
VCCPHY
-
Power VCC of the Ethernet PHY.
C11
PB2
I2C0SCL
I/O
TTL
GPIO port B bit 2.
I/O
OD
I²C module 0 clock.
C12
PB3
I2C0SDA
I/O
TTL
GPIO port B bit 3.
I/O
OD
I²C module 0 data.
D1
PE4
I/O
TTL
GPIO port E bit 4.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
D10
VCCPHY
-
Power VCC of the Ethernet PHY.
D11
VCCPHY
-
Power VCC of the Ethernet PHY.
D12
PB1
I/O
TTL
GPIO port B bit 1.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
E1
PD4
I/O
TTL
GPIO port D bit 4.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
E2
PD5
I/O
TTL
GPIO port D bit 5.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
E3
LDO
-
Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
E10
VDD33
-
Power Positive supply for I/O and some logic.
E11
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
E12
PB0
I/O
TTL
GPIO port B bit 0.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
F1
PD7
I/O
TTL
GPIO port D bit 7.
IDX0
I
TTL
QEI module 0 index.
F2
PD6
I/O
TTL
GPIO port D bit 6.
Fault
I
TTL
PWM Fault.
F3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
F10
GND
-
Power Ground reference for logic and I/O pins.
F11
GND
-
Power Ground reference for logic and I/O pins.
F12
GND
-
Power Ground reference for logic and I/O pins.
G1
PD0
I/O
TTL
GPIO port D bit 0.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
564
April 05, 2010
Texas Instruments-Production Data