LM3S6952 Datasheet, PDF (549/626 Pages) Texas Instruments – Stellaris LM3S6952 Microcontroller

Stellaris® LM3S6952 Microcontroller
21 Signal Tables
21.1
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 21-1 on page 549 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 21-2 on page 553 lists the signals in alphabetical order by signal name.
Table 21-3 on page 557 groups the signals by functionality, except for GPIOs. Table 21-4 on page
561 lists the GPIO pins and their alternate functionality.
100-Pin LQFP Package Pin Tables
Table 21-1. Signals by Pin Number
Pin Number
1
2
3
Pin Name
ADC0
ADC1
VDDA
Pin Type
I
I
-
4
GNDA
-
5
ADC2
I
6
PE4
I/O
7
LDO
-
8
VDD
-
9
GND
-
10
PD0
I/O
PWM0
O
11
PD1
I/O
PWM1
O
12
PD2
I/O
U1Rx
I
13
PD3
I/O
U1Tx
O
14
VDD25
-
Buffer Type^a Description
Analog Analog-to-digital converter input 0.
Analog Analog-to-digital converter input 1.
Power
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
Power
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
Analog Analog-to-digital converter input 2.
TTL
GPIO port E bit 4.
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
TTL
GPIO port D bit 0.
TTL
PWM 0. This signal is controlled by PWM Generator 0.
TTL
GPIO port D bit 1.
TTL
PWM 1. This signal is controlled by PWM Generator 0.
TTL
GPIO port D bit 2.
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
TTL
GPIO port D bit 3.
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
April 05, 2010
549
Texas Instruments-Production Data