GC5016 Datasheet, PDF (79/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
Table 61. Sum Tree Multiplexing Page 0x81 Address 0x11
Rcv Tx
X
C
X
C
X
C
X
C
X
C
X
C
−
−
−
−
−
−
−
−
FIELD
sum_shift
sum_ia
sum_ib
sum_qa
sum_qb
sum_in
sum_of_Ia
sum_of_Ib
sum_of_Qa
sum_of_Qb
BITS Dflt
DESCRIPTION
2..0
Upshifts sum before output (0−7).
4..3
Summing mode off (0), 22 bit sumin (1), bypass (2), 16 bit sumin (3)
6..5
Summing mode off (0), 22 bit sumin (1), bypass (2), 16 bit sumin (3)
8..7
Summing mode off (0), 22 bit sumin (1), bypass (2), 16 bit sumin (3)
9
Summing mode normal (0), quiet (1)
11..10
Sum in mode off (0), IQ multiplexed (1), 16 bit (2), 22 bit (3)
12
Sum tree overflow sticky status bit for Ia
13
Sum tree overflow sticky status bit for Ib
14
Sum tree overflow sticky status bit for Qa
15
Sum tree overflow sticky status bit for Qb
17.18 Receive Sensitivity Registers
The Tables 62, 63,64, and 65 are used to add bit-wise controlled noise to the DDC input path. Normally these bits
are 0, setting a bit to ’1’ adds the Receive LFSR noise generator data to the DDC input data bit.
Rcv Tx
D
X
Table 62. Receive Sensitivity Reduction Path A Page 0x81 Address 0x12
FIELD
rcv_noise_A
BITS
15..0
Dflt
DESCRIPTION
0
Adds noise to input A to desensitize the digital down converters. Must also release pn
generator sync and set test mode to random.
Rcv Tx
D
X
Table 63. Receive Sensitivity Reduction Path B Page 0x81 Address 0x13
FIELD
rcv_noise_B
BITS
15..0
Dflt
DESCRIPTION
0
Adds noise to input B to desensitize the digital down converters. Must also release pn
generator sync and set test mode to random.
Rcv Tx
D
X
Table 64. Receive Sensitivity Reduction Path C Page 0x81 Address 0x14
FIELD
rcv_noise_C
BITS
15..0
Dflt
DESCRIPTION
0
Adds noise to input C to desensitize the digital down converters. Must also release pn
generator sync and set test mode to random.
Rcv Tx
D
X
Table 65. Receive Sensitivity Reduction Path D Page 0x81 Address 0x15
FIELD
rcv_noise_D
BITS
15..0
Dflt
DESCRIPTION
0
Adds noise to input D to desensitize the digital down converters. Must also release pn
generator sync and set test mode to random.
17.19 Receive Input Formatter
The Table 66 values select the complex output bus for each of the 4 DDC channels.
Table 66. Receive Input Formatter Page 0xa1 Address 0x10
Rcv Tx FIELD
BITS Dflt
DESCRIPTION
C
X rinf_sel_A 3..0
Receive input formatting. Normal usage quiet (0), Q part of nonmultiplexed complex (1), IQ
multiplexed (3), real or real portion of nonmultiplexed complex (4), and test (8). Detailed settings
are quiet (0), input to Q (1), input delayed by 1 to I (2), input to I (4), and test to both I and Q (8).
C
X rinf_sel_B 7..4
Same as above, but for path B
C
X rinf_sel_C 11..8
Same as above, but for path C
C
X rinf_sel_D 15..12
Same as above, but for path D
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