GC5016 Datasheet, PDF (58/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
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16.5 Single Strobe, Latch Mode(WRMODE = 1), Control Bus Timing (See Figure 32)
The user can also use the latch mode with a single strobe, as shown in Figure 32.
tCSPW
CE ÓÓÓÓÓÓÓÓÓÓÓÓÓÓ
WR ^{ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ tREC}
tsu(C)
ÔÔÔÔÔÔ
ÔÔÔÔÔÔÔÔÔ
A [4:0]
C [15:0]
tsu(EWC)
WRITE CYCLE − RD HELD LOW
Figure 32. Single Strobe Latch Mode Write Timing
th(C)
16.6 Clocking
The GC5016 uses a single clock, CK to sample, process, and output data. The same clock is used throughout the
chip (gated in some areas to save power). Note that rinf_zpad can be used to allow the input sample rate (in receive)
to be a fraction of the chip clock rate. The, toutf_hold can be used to allow the output sample rate (in transmit) to be
a fraction of the chip clock rate. All channels use the same clock.
16.7 Power-Down Modes
The GC5016 allows software control to power down each of the four channel filters and each of the two cic/mix blocks.
When a block is powered down, control registers are not altered. The state machines and data paths are put into
a reset state. This is used to reduce the core GC5016 power, for unused channels. Channels that have been placed
in power down mode, must be resynchronized after power-on, before use.
16.8 Synchronization
Each GC5016 chip can be synchronized through the use of internal or external signals. There are two sync input
signals, an internal one shot sync generator, or a sync counter. The sync to each circuit can also be set to be always
on (active) or always off (never asserted). The 3-bit sync mode control for each sync circuit is defined in Table 5. A
cmd5016 software command, sync_mode, can be used to setup the channel and start-up synchronization. The value
determined for synchronization, are shown in the TBL file.
In the Down Conversion process, the rinf_zpad_sync, cic filter, pfir filter, and sck_sync will typically require
synchronization. The rinf_zpad_sync is only used if the DDC input uses the receive interpolation or the IQ multiplexed
input modes. The cic_sync is used to select the synchronization of the cic filter decimation. The fir_sync and cic_sync
need to be selected to a common sync signal. The fir_sync selects the synchronization signal for the filter’s
decimation, address generators, and state machines. The coef_sync is used if multiple coefficient banks are desired,
and a sync is used for selection. The sck_sync is used to synchronize the divided clock (if used) for the Receive
Output interface.
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