GC5016 Datasheet, PDF (53/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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15 GC5016 IN TRANSCEIVER MODE
GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
The GC5016 can also be configured in a transceiver mode as shown in Figure 3, where channels A and B function
in up-conversion mode and channels C and D function in down-conversion mode. The channel details for A and B
are identical to those described above for the up-conversion mode. The channel details for C and D are identical to
those above for down-conversion mode. Two input ports and two output ports are available each for the
up-conversion channels and down-conversion channels.
The down-conversion interfaces are described in the Receive (DDC) section. The up-conversion interfaces are
described in the Transmit (DUC) section. The Sumin port function is not available in transceiver mode.
The splitiq_AB, and splitiq_CD cmd5016 variables are used for special Transceiver conditions. In this example, the
Channel A and B are configured as a splitIQ DUC section, and Channels C and D are configured as individual DDC
channels.
16 GENERAL GC5016 FEATURES
16.1 Control Interface
Writing control information into control registers configures the GC5016. The control registers are grouped into eight
global registers and 88 pages of registers, each page containing up to 16 registers. The global registers are accessed
as addresses 0 through 0xF.
The non-global pages of registers are accessed as addresses x10 through x1f. The control register at global address
0x2 is the page register. The value written to the page register selects which page is accessed for addresses 16(x10)
through 31(x1f).
The contents of the control registers and how to use them are described in tables 8 through 67 later in the data sheet.
The registers are written to or read from using the C[15..0], A[4..0], CE, RD, and WR pins. Each control register has
been assigned a unique address within the chip. This interface is designed to allow the GC5016 chip to appear to
an external processor as a memory mapped peripheral (the pin RD is equivalent to a memory chip’s OE pin).
The dual strobe and single strobe cycles are selected based on the RD pin:
1. If the RD and WR pins are used as separate strobes, this is the dual strobe mode. CE and RD are required for
the read cycle. CE and WR are required for the write cycle.
2. If the RD pin is grounded, this is considered the single strobe mode. The level of the WR pin while the CE pin
is active, determines the read or write cycle.
Write timing is controlled by the WRMODE pin:
1. If the WRMODE pin is ’0’, the write timing is edge based. The data bus must be stable for a setup time before
and a hold time after (CE or WR) goes high
2. If the WRMODE pin is ’1’, the write timing is latch based. The data bus must be stable for a setup time before
(CE and WR) goes low and a hold time after (CE or WR) goes high.
NOTE:The suggested external processor interface is dual strobe and edge-WRMODE, where the WRMODE
pin is connected to GND.
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