GC5016 Datasheet, PDF (67/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
Table 10. FirA Control RAMs
BLOCK
FirA
FirB
FirC
FirD
PAGES
00−1F
20−3F
40−5F
60−7F
DESCRIPTION
Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for A
Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for B
Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for C
Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for D
Table 11 lists the control registers for FirA.
PAGE
0−F
10
11
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
14
Table 11. FirA Control Registers
ADDRESS
10−1F
10−1F
10−1F
10
11
12
13
14
15
16
17
18
19
1a
10
11
12
13
14
15
16
17
18
19
1a
1b
1c
1d
1e
1f
10
11
12
13
14
15
REGISTER DESCRIPTION
FIR coefficients
Swap ram contents
BE ram contents
Coefficient address generator
Common address generator
Forward read address generator
Forward write address generator
Backward read address generator
Backward write address generator
Backward end cell read address generator
Backward end cell write address generator
Forward write strobe
Backward write strobe
Backward end cell read bypass
Transmit input formatter
Transmit frame strobe controls
Transmit frame counter
Gain 16 LSB’s
Gain controls
AGC minimum adaptation limit
AGC maximum adaptation limit
AGC counts and threshold
AGC loop gains
AGC gain read back
Power meter least significant 16 bits
Power meter most significant 16 bits
Power meter status
Power meter Integration time
Receive output formatter
Receive checksum
FIR swap ram controls
FIR accumulator controls
FIR output control
FIR sync count
FIR clock
Channel syncs
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