GC5016 Datasheet, PDF (45/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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Real In
AI
AFS
ACK
Imag In
BI
BFS
BCK
GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
NCO
TINF
GAIN
PFIR
I(2k)
Dual CIC
I(2k+1)
TDM
Broadcast
Cross connect for double rate
TINF
GAIN
PFIR
Q(2k)
Dual CIC
Q(2k+1)
NCO
C
I(2k)
Q(2k)
SUM
and
FORMAT
I(2k+1)
Q(2k+1)
IFLG
AO [15:0]
BO [15:0]
CO [15:0]
DO [15:0]
D
Figure 23. Double Rate Mode Transmit Channel
14.8 Transmit Output Interface
The complex mixer outputs are rounded to 21 bits and sent to the sum tree and transmit output formatter. The sum
tree optionally adds together DUC channel outputs, and the transmit output formatter rounds the results and formats
them for output on the 16 bit output ports: AO, BO, CO, and DO. The data pins for the output ports are AO[15..0],
BO[15..0], CO[15..0], and DO[15..0].
The rounded 21-bit mixer outputs can either be sent to separate output ports or summed into one or two output signals
in a sum tree. The summed signal can also be added to data from an external source such as other GC5016 chips.
In this case, ports CO and DO function as sum input ports and are not available for signal output. The sum input path
and sum output path are expected to be configured the same in all GC5016 chips in a summing chain except for
possible rounding in the final chip.
The possible output formats and the cmd5016 keyword settings that are used to select them are shown in Table 3.
The possible output modes are identified by the ”Rate”, ”Real or IQ”, and ”Sum” columns.
The ”Rate” can be either full, half or double. Full is the most common mode and indicates that a new sample is output
every clock cycle (CK). Half means that complex samples are output at half the clock rate in an interleaved I followed
by Q format. The IFLAG output signal identifies the I sample. Double means that the sample rate is twice the clock
rate so that two time samples are output every clock cycle: Even time samples on one port, odd on another.
The ”Real or IQ” mode identifies if the output is real or complex. If the output is complex, then the I and Q halves
can either come out on separate ports or interleaved onto a single output port as specified by the ”Rate” mode.
The ”Sum” mode can either be none, pairs or all. The ”none” mode means that each DUC channel is output on its
own port and is not added to the other DUC outputs. The ”pairs” mode means that the outputs from DUC channels
A and B are added together and the outputs from DUC channels C and D are added together. The ”all” mode means
that all of the DUC channels are added together.
Table 3 is divided into sections that show settings for:
D Using standard resolution output word size (tout_res=0 for16 bits or less)
D Using wide resolution word size (tout_res=1 for up to 22 bits). Output ports AO and BO are merged and output
ports CO and DO are merged to give 22 bit outputs in the wide resolution mode.
D Using external sum IO paths (tout_sumio=0 for no sumio, tout_sumio=1 for sumio turned on). Ports CO and DO
become input ports when the sumio path is turned on.
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