GC5016 Datasheet, PDF (61/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
16.9.2 Multiple GC5016 Chips Using SO From a Master GC5016 Chip
This procedure works if multiple GC5016 chips need to be synchronized. This assumes that the sync output pin (SO)
from the master GC5016 chip is connected to the SIA input pin on all GC5016 chips including the master chip.
1. Reset the chip by writing 0xFF00 to address 0 of all chips.
2. Disable all outputs except SO, by writing 0x100 to address 3 of all chips.
3. Force the one-shot to be a pulse and use the one shot to drive SO by writing 0x04 to address 1 in all chips.
4. Load the configuration generated by the cdm5016 program to all chips.
NOTE:All sync controls except for SO, should be set to 2 so that they are controlled by the SIA input sync.
This can be done by adding these lines to the cmd5016 input file:
soB_sync 4
fir_sync 2
sck_sync 2
nco_sync 2
cic_sync 2
5. Clear the reset by writing 0x100 to address 0 of all chips.
6. Pulse the syncs by writing 0x14 to address 1 of the master chip.
NOTE:The above procedure is selected by setting pseudo-command sync_mode to’ 5’.
16.9.3 Multiple GC5016 Chips Using an External Sync
Same as above, except the SIA input is tied to an FPGA or other sync source.
1. Reset the chip by writing 0xFF00 to address 0 of all chips.
2. Disable all outputs except SO, by writing 0x100 to address 3 of all chips.
3. Drive the SIA inputs low (active) using the external sync source.
4. Load the configuration generated by the cdm5016 program to all chips.
NOTE:All sync controls should be set to 2, so that they are controlled by the SIA input sync.
This can be done by adding these lines to the cmd5016 input file:
soB_sync 2
fir_sync 2
sck_sync 2
nco_sync 2
cic_sync 2
5. Clear the reset by writing 0x100 to address 0 of all chips.
6. Release the syncs by setting SIA high (inactive).
NOTE: SIA is clocked into the GC5016 chips by CK and the signal must meet the specified setup and hold times for all
of the GC5016 chips.
NOTE:The above procedure is selected by setting pseudo-command sync_mode to ’5’. Only the master
GC5016 has the Sync Output tied back to the FPGA. The other GC5016s have their SIAs tied to the FPGA
outputs.
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