GC5016 Datasheet, PDF (41/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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14.3 Gain
GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
Each 20-bit input sample is multiplied by a 19-bit gain word. The 16 gain LSB’s are stored in one register, gain_lsb
and three MSB’s in another, gain_msb. The gain adjustment is GAIN/212, where the gain word (gain) ranges from
0 to (+219 − 1). Negative gains are not allowed. This gives a 0.002-dB gain adjustment resolution. Setting gain_msb
and gain_lsb to zero clears the channel input. A different gain can be specified for each channel. The gain values
are usually set using the overall_gain keyword in the cmd5016 software.
The gain values are double buffered and are transferred to the active register at the first I sample after sync
(gain_sync). The gain block for each up-conversion channel contains a dedicated 20x20 multiplier to apply fine gain
control. The result is rounded to 18 bits, limited to one for non-symmetric filters or one-half for symmetric filters, and
sent to a programmable filter. This is controlled manually using gain_half or the software calculates it automatically.
14.4 Programmable Finite Impulse Response Filter (PFIR)
The interpolating PFIR filter consists of an input swap RAM, 15 common-programmed FIR filter cells, a special 16
FIR end cell, a control and address generator block, a final accumulator, and an output gain shift, round, and limit
block (see Figure 20). The PFIR can process real or complex data.
The DDC and DUC share the same PFIR. The configuration of the PFIR and surrounding blocks, changes some of
the functions( ie DDC decimation, DUC interpolation). The sections in the PFIR filter cells are:
16x18-bit (16 words with 18-bit width) forward tap delay RAM,
backward 16 x 18-bit tap delay RAM (used for symmetric filters),
pre-adder with 18-bit output (the reverse input is 0 for non-symmetric filters),
16x16-bit filter coefficient RAM,
16-bit x 18-bit multiplier,
38-bit sum chain.
The output of the sum chain is sent to an accumulator with 42-bit output and is then shifted up 0−7 bits, round and/or
limited with a 20-bit output that is sent to the AGC.
The PFIR sections are programmed independently for each channel. The filter coefficients can be arranged in banks
allowing the user to change between multiple filter sets rapidly and synchronously. Two sets of coefficients might be
used in an adaptive application, where one set is being used while the other set is being updated. On each clock cycle
the filter computes 16 taps (31 if symmetric). The number of clocks between PFIR outputs is cic_int.
If the data stream is complex then half the clock cycles are used computing the I output and half are used computing
the Q output. The tap delay line limits the filter length to 256 if non-symmetric and 511 if symmetric (half this with
complex data streams). The maximum number of taps is determined by the cmd5016 program. It can be estimated
by:
ntaps = sym x min(256, (16 x fir_int x int (cic_int/(cmplx*fir_nchan) − odd)))
where:
cmplx = 1 for real data (or splitiq) and 2 for complex
sym = 1 for nonsymmetric and 2 for symmetric
odd = 1 for symmetric filters
fir_nchan = 1 for up and down conversion.
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