GC5016 Datasheet, PDF (66/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
17.3 DUC Mode Pseudo-Fields
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mode AB(CD) transmit − identifies DUC mode
tinf_cmplx, tinf_tdm − identifies the Transmit Input Formatter mode
tinf_fs_dly − customer logic Transmit Input Formatter timing offset
splitiq, splitiqAB, splitiqCD − determine the 2channel or 4 channel mode
gain, overall_gain − manual gain settings
bypass_fir, fir_int, fir_diff, fir_nchan, fir_coef − determine the PFIR mode, and filter taps
bypass_cic, cic_int − determines the dual CIC filter decimation
freq, fck, bypass_mix − determine the complex mixer freq_msb, freq_mid, freq_lsb settings
tout_sumin − determines if the COut and DOut are used as the sum input port, activates sum input mode
tout_nsig − determines the two internal sum logic sets of A,B,C, and D channels
tout_rate, tout_cmplx, tout_res − determines the DUC output modes, and signal to pin mapping
17.4 Control Registers
This section describes the control registers of the GC5016. The control register addressing is divided into two
sections:
Page − the value of global address 2
Address − the hexadecimal value of the five address pins
The Global registers are accessed through addresses 0 through 0xF. The paged registers are accessed through
addresses x10 through 0x1F.
Table 8 provides an overview of the page allocations. FirA−D, cicAB, and cicCD are hardware blocks that contain
the signal processing blocks listed in Table 8.
The register values are not changed by the hardware-reset pin, software master reset, block reset, or clock loss. A
global register 0 (internal reset and power down) is set at power up (but not by any reset action). Global register 3
(output enables) is cleared at power up.
Table 8. Map of Control Pages
BLOCK
FirA
FirB
FirC
FirD
cicAB
cicCD
PAGES
00−1F
20−3F
40−5F
60−7F
80−81
a0−A1
DESCRIPTION
Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for A
Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for B
Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for C
Transmit input formatter, gain, PFIR, AGC, power meter, receive output formatter for D
CIC, NCO, mixers for channels A and B, common transmit blocks
CIC, NCO, mixers for channels C and D, common receive blocks
Table 9 lists the global registers in the chip.
Table 9. Global Control Registers
PAGE
Global
Global
Global
Global
ADDRESS
0
1
2
3
REGISTER DESCRIPTION
Reset and clock control
General sync
Page and revision
Output enables
Table 10 lists the 4 FIR & Control blocks. Table 11 lists the registers in FirA. FirB, FirC, and FirD have Identical
registers with page offsets of 20, 40, and 60 respectively.
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