GC5016 Datasheet, PDF (13/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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13.2.3 Receive Interpolation
GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
If the GC5016 CK rate divided by the input sample rate is an integer ratio, receive interpolation can be used (see
Figure 4). In this case, the chip can be programmed to insert 0−15 zeros (rinf_zpad) between input samples. This
effectively interpolates the signal up by rinf_zpad+1. The higher CK rate means the chip is operating faster, so the
PFIR has more multiplication operations available per sample. It also allows greater flexibility in selecting the output
sample rate since:
Fs_out=Fck / (cic_dec x fir_dec), where Fck=Fadc x (1+rinf_zpad).
One sample is registered while the data input on the other rinf_zpad clocks are zeroed. The user has control over
which sample is used through rinf_zpad_sync. The zpad selected sync encounters a two CK cycle delay, then loads
a counter. When the counter reaches the terminal count, it is reloaded and a data sample is kept. All other data
samples are zeroed. The sample occurring two plus (rinf_zpad + 1) clock cycles after the sync is used, while the other
samples are ignored. The sync input may be periodic in any multiple of (rinf_zpad+1) or may occur just once.
If I and Q are time multiplexed, then the sync should be coincident with the Q sample.,
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