GC5016 Datasheet, PDF (62/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
16.10 Diagnostics
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The GC5016 provides self-test capability by providing a pattern generator at the inputs, a specific signal processing
setup condition, a linear feedback shift register LFSR to develop an output results, and a checksum register read
by the local bus. A general timer is used to sequence the load, run for n cycles, and capture the test results.
The diagnostic tests are provided in the gc5016 developer’s toolkit. There are 5 different tests, a local bus interface
test, and 4 separate checksum tests. More details on these tests are given in the application notes at the end of this
document.
The LFSR generator for the DDC inputs has specific register variable settings. The rinf_diag register variable selects
the diagnostic source, which can generate a linear feedback sequence, a constant, or a ramp. The
rinf_sel_[portA,B,C,D] selects the receiver input-bus, or a diagnostic input for each DDC input bus. The
cksum_sync_front register value selects the synchronization source for the pattern generator.
Once the local bus registers have been programmed, the general timer starts, which releases the GC5016 to perform
the test. The LFSR inputs are processed in the DDC channel, and after the gain output, the IQ data is input to the
receive checksum logic. The receive checksum computes another LFSR sequence, and when the general timer has
counted the number if tests cycles to be performed, the LFSR output is registered in the checksum register. Each
general timer cycle, the checksum generator is recycled to start the test.
There is a separate pattern generator at the transmit inputs, which can generate a linear feedback sequence or a
constant. The register variable tx_pat_gen controls the Transmit diagnostic source. The register variable tinf_src
selects the TINF data port input or the diagnostic input.
The same type of test cycle can be performed from the Transmit input LFSR generator, through the Transmit DUC
logic, to the Transmit output LFSR sequence, to the local bus register. At the start of the checksum test, the general
timer sync clears the cksum_sync_back selection synchronizes the rcv_checksum register feedback. The general
timer interval IQ events are processed in the checksum logic. At the completion of the general timer, the last LFSR
calculation is latched in the checksum register.
The cksum_sync_front selection synchronizes the transmit_cksum register feedback. The number of internal IQ
events are processed in the checksum logic, based on the general timer value. When the general timer completes,
the last LFSR calculation is latched in the checksum register.
The NCO must be sync’d with the data pattern (so the accumulated phase always starts at zero). The dither sync
must either be set to always on (thus freezing the dither) or sync’d to the sync source. The user should wait for at
least four sync periods to allow the checksum to stabilize before reading the checksum.
The checksum and console diagnostic tests are further described in the application section.
16.11 JTAG
The GC5016 supports JTAG with a 5-pin interface. The JTAG implementation supports the standard boundary scan
(used for board test), and chip identification. A BSDL file is available on the web. The GC5016 identification string
is a 1 followed by an 11-bit manufacturer number (0x8C), a 16-bit chip number (5016 = 0x1398), and a 4-bit revision
number (currently a 1).
The TRST inverted pin is not used on 4 wire JTAG testers. This pin should have at least a 1-kΩ pull-up resistor to
3.3 V during JTAG operation.
NOTE:The TRST pin must be connected to GND during normal operation.
16.12 Mask Revision Register
The mask revision register contains a simple 8-bit code that changes with any mask changes which may impact
software, so that users can deploy software that tests for which revision and changes the behavior accordingly. The
current revision value is 1.
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