GC5016 Datasheet, PDF (52/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
www.ti.com
14.10.4 Output Rounding and I/Q Multiplexing
The data on paths A and B next enter mux and round. Multiplexing allows I and Q to be time multiplexed onto the
same set of pins. Effectively, this decimates the signal by two and the sync source for this decimation is the cic_sync.
Finally, toutf_rndAB controls rounding of bits from the bottom, so the resulting word is 12 (3), 14 (2), 16 (1), or 22
(0) bits. Bits below the round point are forced to zero. After rounding, the data is hard limited. Paths ia, qa, ib, and
qb are 22 bits.
Processing on paths C and D is similar. If channels are added together, channels C and D are routed up and added
into paths A and B. If all four channels are output separately then the mux, round, and delay blocks on paths C and
D are used. The C and D data is delayed to match hardware pipelining delay on paths A and B. Since there is no
summing gain, a fixed upshift of one bit is provided to compensate for the one bit of headroom in the mixer output.
The blocks can either output the real data or IQ multiplexed (toutf_halfcmplx_CD=1). Paths ic and id out of these
blocks are limited to 16 bits, since that matches the size of the output ports. Control toutf_rndCD determines the
round. Since the path is limited to 16 bits, both toutf_rndCD=0 and toutf_rndCD=1 round to 16 bits. If paths C and
D are unused here (for example when adding paths C and D into paths A and B), then setting toutf_quiet_CD forces
an overflow condition, thus holding the bus constant (and quiet).
14.10.5 Transmit Output Multiplexing
The final block can invert the msb (toutf_offsetbin) for systems that prefer offset binary output to two’s complement.
Port AO always outputs ia.
Port BO can output zeros (toutf_bo=0), ib (toutf_bo=1), qa (toutf_bo=2), the lsb’s of ia (toutf_bo=4), or the
complement of AO (toutf_bo=8). Setting 4 is used to support output word sizes greater than 16 bits. If 22 bits are
output, then AO gets bits 21..6, while BO[15..10] gets bits 5..0. The remainder of BO is zero. Finally, setting 8 sets
BO to be the complement of AO. This can be used together with external resistor packs to create LVDS outputs. Other
settings for toutf_bo are undefined.
Port CO can output zeros (toutf_co =0), ic (toutf_co =1), ib (toutf_co =2), or qa (toutf_co =4). Other settings for
toutf_co are undefined.
Port DO gets zeros (toutf_do =0), id (toutf_do =1), qb (toutf_do =2), ib lsb’s (toutf_do =4), qa lsb’s (toutf_do =8), or
CO complement (toutf_do =16). Other settings for toutf_do are undefined.
14.11 Overall Gain in Transmit Mode
The overall gain in the transmit mode is defined below. The gain is normally set using the overall_gain keywork in
the cmd5016 configuration software. The overall gain is set relative to the MSB of the input data to the MSB of the
output data. For example, if overall_gain is set to 1.0, then a full scale input sample will result in a full scale output
sample. This allows the user to set the gain based upon the desired input and output crest factors. Note that the gain
is for each channel, if multiple DUC channels are added together then the overall_gain should be decreased to
compensate for the increased crest factor. See the ”DUC Mode GAIN” application note for complete details.
The gain of the chip is a function of the input gain setting (G), the sum of the programmable filter coefficients, the
filter gain (fir_shift), the amount of interpolation in the CIC filters (cic_int), the scale circuit settings in the CIC filter
(cic_shift), and the sum tree scale factor (sum_shift). The overall gain (22-bit sumio mode) is:
NJǒ Ǔǒ Ǔ Nj GAIN +
G
4096
PFIR_SUM
fir_int 2^21*fir_shift
cic_int^{(5*cic_xmt_5stg)} 2^cic_shift*41
2^sum_shift*6
where cic_int, G, PFIR_SUM, and fir_shift can be different for each channel, but sum_shift is common to all channels.
The term inside { } should be less than or equal to one. For no sumio or 16 bit sumio modes, the gain is:
NJǒ Ǔǒ Ǔ Nj GAIN +
G
4096
PFIR_SUM
fir_int 2^21*fir_shift
cic_int^{(5*cic_xmt_5stg)} 2^cic_shift*41
2^sum_shift*3
NJǒ Ǔǒ Ǔ Nj GAIN +
G
4096
PFIR_SUM
fir_int 2^21*fir_shift
cic_int^{(5*cic_xmt_5stg)} 2^cic_shift*41
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