English
Language : 

GC5016 Datasheet, PDF (69/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER
www.ti.com
17.5 Global Registers
GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
The following tables describe the various bit fields contained in each of the global control registers.
Table 14. Global Register Reset and Clock Control Address 0x0 Bits 15.8 Set at Power Up
Rcv Tx
FIELD
BITS Dflt
DESCRIPTION
− − ck_loss_status 1..0
DD
en_ck_loss
8
1 Enable clock loss detection. Highly recommended.
C C pwr_dwn_fir_A
9
Power down PFIR in A. Power down puts the GC5016 section in reset and disables the clock.
It does not reset the control registers.
C C pwr_dwn_fir_B 10
Power down PFIR in B
C C pwr_dwn_fir_C 11
Power down PFIR in C
C C pwr_dwn_fir_D 12
Power down PFIR in D
C C pwr_dwn_cic_AB 13
Power down cic/mix for A and B
C C pwr_dwn_cic_CD 14
Power down cic/mix for C and D
CC
master_reset
15
Power down all sections
RCV TX
DD
−−
FIELD
soB_sync
one_shot
Table 15. General Sync Global Address 0x1
BITS Dflt
2..0 2
4..3
DESCRIPTION
Signal selection for sync_out_B
One shot control. (=0) Armed issue one shot when LSB goes high; (=1) issues one shot on
transition of LSB to high safe state to be left in; (=2) level output 0; (=3) level output 1
Rcv Tx
−−
−−
FIELD
page
chip_rev
Table 16. Page and Revision Global Address 0x2
BITS Dflt
DESCRIPTION
7..0
Page register
15..8
Chip revision. Read only. Currently 1.
Rcv Tx
CC
CC
CC
CC
CC
CC
CC
CC
CC
DD
DD
DD
DD
XD
Table 17. Output Enables Global Address 0x3 Cleared at Power Up
FIELD
en_AO
en_AFS
en_BO
en_BFS
en_CO
en_CFS
en_DO
en_DFS
en_soB
ckp_A
ckp_B
ckp_C
ckp_D
sumin_clr
BITS Dflt
DESCRIPTION
0
Enable data output AO
1
Enable frame strobe and output clock for A
2
Enable data output BO
3
Enable frame strobe and output clock for B
4
Enable data output CO
5
Enable frame strobe and output clock for C
6
Enable data output DO
7
Enable frame strobe and output clock for D
8
Enable sync_out_B and iflag
9
0 Invert ACK
10 0 Invert BCK
11 0 Invert CCK
12 0 Invert DCK
13 0 Force sumin port to zero
69