GC5016 Datasheet, PDF (71/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
17.9 Programmable FIR, Gain, Transmit Input, and Receive Output Control Registers
The following tables detail the various control registers for a single PFIR filter. Note that the configuration software
calculates these registers. The PFIR has several sets of memories that are synchronized to read the data to be
filtered, and the coefficient memory. The Common Address Generator is used to read from the Forward and Reverse
Delay memory in each cell. This represents the data to be filtered. Different filtering modes, can have I or Q data at
different offset positions. The Coefficient Address generator is used to read the coefficient memory.
The Forward Read address and Forward Write address are used at the end of each computational cycle, to pass
the Forward Delay data between the FIR cells. The Forward Write strobe indicates the times within the PFIR
calculates that the data is written to the next cell.
The Backward Read address, Backward Write address, Backward End Cell Read address, Backward End Cell Write
address, and Backward End Cell Read Bypass are used to develop the address to pass the reverse delay line data
from the 16^th FIR cell back towards the 1^st FIR cell. The Backward Write strobe indicates the times within the PFIR
calculates that the data is written to the next cell.
Table 19. Coefficient Address Generator Page 0x12 Address 0x10
Rcv Tx
FIELD
E
E coef_ofsc
E
E coef_modc
E
E coef_repc
E
E coef_sym
E
E coef_zerofr
BITS Dflt
3..0
7..4
11..8
12
13
DESCRIPTION
FIR coefficient address offset
FIR coefficient modulo count
FIR coefficient repeat count
FIR hardware exploits symmetry (1) or not (0)
FIR zero forward read
Rcv Tx
E
E
E
E
E
E
E
E
Table 20. Common Address Generator Page 0x12 Address 0x11
FIELD
agen_recr
agen_depd
agen_modd
agen_togen
BITS Dflt
3..0
7..4
11..8
12
DESCRIPTION
FIR recirculate count
FIR depth count
FIR modulo count
FIR toggle enable for back end read and write
Table 21. Forward Read Address Generator Page 0x12 Address 0x12
Rcv Tx
FIELD
E
E fragen_soff
E
E fragen_srecr
E
E fragen_sdepd
E
E fragen_stepn
BITS Dflt
3..0
7..4
11..8
15..12
DESCRIPTION
FIR forward read address generator offset
FIR forward read address generator recirculate count
FIR forward read address generator depth count
FIR forward read address generator step
Table 22. Forward Write Address Generator Page 0x12 Address 0x13
Rcv Tx
FIELD
E
E fwagen_soff
E
E fwagen_srecr
E
E fwagen_sdepd
E
E fwagen_wrecrl
BITS Dflt
3..0
7..4
11..8
15..12
DESCRIPTION
FIR forward write address generator offset
FIR forward write address generator recirculate count
FIR forward write address generator depth count
FIR forward write address generator step
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