GC5016 Datasheet, PDF (23/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

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GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
Example using manual one shot firing:
1. Sync integration counter
2. Wait for ready bit to be 1 (eight clocks or less depending on sync source)
3. Arm and fire one shot to clear ready
4. Wait for ready bit to be 1
5. Read power LSB
6. Read power MSB
7. Arm and fire one shot to clear ready
8. Check to be sure missed bit is not set
9. Go to step 4
NOTE: The too_soon bit is never set if ready is active when one shot fires.
13.9 Gain, Rounding, and IQ/AGC Multiplexing
The 20-bit PFIR output is multiplied by the (manual + AGC) 19bit gain value (see Figure 12). The gain adjusted output
data is saturated to full scale and then rounded to between 4 and 20 bits in steps of one bit. The round circuit provides
a round-to-even and shift of the data into the specified upper bits of the 20 bit DDC output. If selected, a special output
multiplexing occurs to output the gain, I, and Q data. See Table 2. In the splitIQ mode, the I or Q is rounded and output.
The DDC Output formatter converts the I, Q interleaved and AGC gain into the selected output format.
13.10 Automatic Gain Control (AGC)
The GC5016 automatic gain control circuit is shown in Figure 12. The basic operation of the circuit is to multiply the
20-bit input data from the PFIR by a 19-bit gain word that represents a gain or attenuation in the range of 0 to 128.
The gain format is mixed integer and fraction. The 7-bit integer allows the gain to be boosted by up to a factor of 128
(42 dB) in .33db steps. The 12-bit fractional part allows the gain to be adjusted up or down in steps of one part in
4096 or approximately 0.002 dB. If the gain integer and fractional value is less than 4096, this is attenuation. The
gain equation is:
gainAv = ( (gain_msb × 65536) + gain_lsb ) / 4096
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