GC5016 Datasheet, PDF (26/88 Pages) Texas Instruments – WIDEBAND QUAD DIGITAL DOWN CONVERTER/ UP CONVERTER

GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
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The clocks [A..D]CK for each port are generated by dividing the GC5016’s main clock CK by a programmable divider
for each port. Programming the divided port clock establishes the output rate for this port. The clock dividers can be
synchronized by the methods described in the Synchronization section. The polarity of each divided port clock
[A..D]CK] is user programmableThe clock, data and Frame Strobe outputs are output after the rising edge of the CK
clock. Figure 13 shows the t_d and t_h(o) timing between the CK and the Output (Out[ ]) Bus.
The divided port clocks [A..D]CK are output by the GC5016 as data signals, and therefore change nearly
simultaneously with the frame strobes and the output data pins. The divided clocks typically transition 0.5ns after
the frame strobe and the output data due to the xor gate for clock polarity. When ck_pol is 0 data transitions just before
the rising edge of [A..D]CK ,the falling edge of [A..D]CK should be used. If ck_pol is 1, then the rising edge should
be used. The serial clock output is valid starting six clocks after the incoming sync selected by sck_sync (see
Figure 14).
The frame strobe is one sck period in width. The divided port clock (sck_div + 1) should be a submultiple of the
decimation ratio (cic_dec × fir_dec). Otherwise the frame period varies between X sck periods and X+1 sck periods.
The output port data can be sampled on the rising edge of CK after the Frame Strobe is asserted. The Time Division
Multiplexed Output, and Interleaved IQ output require multiple samples to capture the output data. The customer
logic must generate the multiple cycles after the Frame Strobe is received.
The divided port clock can be used to hold the output data across several CK cycles. It is easier to design the logic
interfacing with the GC5016 receiver output if there is an integer number of channel divided clocks in the output frame.
A combination of the CK and channel clock can be used to register the GC5016 output data.
NOTE:The cmd5016 programming tool calculates the DDC output format settings. If the DDC output uses multiplexed
data, and the output frame has no idle time, an error may occur. The cmd5016 programming tool may issue a warning
for this configuration. The output mode needs to have at least one idle clock cycle, or needs timing verification with the
actual configuration.
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