DRV8305_15 Datasheet, PDF (45/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

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10 Layout
DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
10.1 Layout Guidelines
Use the following layout recommendations when designing a PCB for the DRV8305.
• The DVDD and AVDD 1-μF bypass capacitors should connect directly to the adjacent GND pin to minimize
loop impedance for the bypass capacitor.
• The CP1 and CP2 0.047-μF flying capacitors should be placed directly next to the DRV8305 charge pump
pins.
• The VCPH 2.2-μF and VCP_LSD 1-μF bypass capacitors should be placed close to their corresponding pins
with a direct path back to the DRV8305 GND net.
• The PVDD 4.7-μF bypass capacitor should be placed as close as possible to the DRV8305 PVDD supply pin.
• Use the proper footprint as shown in the Mechanical, Packaging, and Orderable Information section.
• Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the DRV8305
GH_X to the power MOSFET and returns through SH_X. The low-side loop is from the DRV8305 GL_X to the
power MOSFET and returns through SL_X.
10.2 Layout Example
Figure 17. Layout Recommendation
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