DRV8305_15 Datasheet, PDF (23/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

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DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.
7.3.10.2 Shoothrough Protection
DRV8305 integrates analog and digital monitors to prevent shoot-through in the external FETs.
• An Internal handshake through analog comparators is performed between high-side and low-side FETs
during switching transition.
• A minimum dead time (digital) of 40 ns is always inserted after a successful handshake. This digital dead-time
is programmable and is in addition to the time taken for the handshake.
7.3.10.3 VDS Sensing – External FET Protection and Reporting (OC Event)
To protect the external FETs from damage due to high currents, V_DS sensing circuitry is implemented in the
DRV8305.
The V_DS sensing is implemented for both the high-side and low-side MOSFET through these pins:
• High-side MOSFET: V_DS measured between VDRAIN and SHX pins
• Low-side MOSFET: V_DS measured between SHX and SLX pins
Based on R_DS(on) of the power MOSFETs and the maximum allowed I_DS, a voltage threshold can be calculated,
which when exceeded, triggers the V_DS protection feature.
This voltage threshold level is programmable through SPI command and may be programmed during operation if
needed.
The V_DS protection logic also has an adjustable blanking time and deglitch time to prevent false trips.
V_DS blanking time (t_BLANK): This time is inserted digitally and is programmable. The t_BLANK time is a delay inserted
at each output after that particular output has been commanded to turn ON. During t_BLANK time, the VDS
comparators are not being monitored in order to prevent false trips when the FETs first turn ON.
V_DS deglitch time (t_VDS): This time is inserted digitally and is programmable. The t_VDS time is a delay inserted after
the VDS sensing comparators have tripped to when the protection logic is informed that a VDS event has
occurred.
Note that the dead time and blanking time are overlapping counters as shown in Figure 9
INx_x
Gx_x
1 _{Input Signal}
2 _{Output Slew}
3 _{Expiration of Blanking}
t_Dead
t_BLANK
12
t_deglitch
3
Figure 9. VDS Protection Timing
Three overcurrent responses are possible depending on the configuration option selected through SPI.
• V_DS event latch shutdown mode
When a VDS event occurs, device will pull all outputs low in order to take all six external FETs into high-
impedance mode. The Fault will be reported on nFAULT and details of the FET that reported the fault can be
read back through SPI.
• V_DS event Reporting only mode
In this mode, VDS event will be reported on the nFAULT pin and the SPI register. Gate drivers will continue
to operate.
• V_DS event disable mode
Device ignores all the V_DS event detections and does not report them.
Copyright © 2015, Texas Instruments Incorporated
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