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DRV8305_15 Datasheet, PDF (18/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator
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DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
AB
AB_CB
CB
CB_CA
CA
CA_BA
BA
BA_BC
BC
BC_AC
AC
AC_AB
Align
Stop
Table 3. 1-PWM Active Freewheeling
INLA : INHB : INLB : INHC
0110
0101
0100
1101
1100
1001
1000
1011
1010
0011
0010
0111
1110
0000
AH
PWM
PWM
LOW
LOW
LOW
LOW
LOW
LOW
LOW
PWM
PWM
PWM
PWM
LOW
AL
!PWM
!PWM
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
!PWM
!PWM
!PWM
!PWM
LOW
BH
LOW
LOW
LOW
LOW
LOW
PWM
PWM
PWM
PWM
PWM
LOW
LOW
LOW
LOW
BL
HIGH
HIGH
HIGH
HIGH
LOW
!PWM
!PWM
!PWM
!PWM
!PWM
LOW
HIGH
HIGH
LOW
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CH
LOW
PWM
PWM
PWM
PWM
PWM
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
CL
LOW
!PWM
!PWM
!PWM
!PWM
!PWM
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
AB
AB_CB
CB
CB_CA
CA
CA_BA
BA
BA_BC
BC
BC_AC
AC
AC_AB
Align
Stop
Table 4. 1-PWM Diode Freewheeling
INLA : INHB : INLB : INHC
0110
0101
0100
1101
1100
1001
1000
1011
1010
0011
0010
0111
1110
0000
AH
PWM
PWM
LOW
LOW
LOW
LOW
LOW
LOW
LOW
PWM
PWM
PWM
PWM
LOW
AL
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
BH
LOW
LOW
LOW
LOW
LOW
PWM
PWM
PWM
PWM
PWM
LOW
LOW
LOW
LOW
BL
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
CH
LOW
PWM
PWM
PWM
PWM
PWM
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
CL
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
7.3.3 Charge Pump
A regulated triple charge pump scheme is used to create sufficient VGS to drive standard FETs under low voltage
operation.
The high-side FETs are directly driven by the tripler charge pump output while the low-side FETs are driven by a
voltage that is internally regulated but derived from the tripler charge pump. This allows both the high side and
low side to maintain sufficient VGS through low voltage transients. This topology also supports 100% duty cycle
operation.
Between 4.4 to 18 V the charge pump regulates the voltage in tripler mode; beyond 4.4 to 18 V, it switches over
to doubler mode until the operating max voltage. The charge pump is monitored for undervoltage and
overvoltage conditions to prevent underdriven or overdriven FET conditions.
7.3.4 Gate Driver Architecture
The DRV8305 gate driver is a complimentary push-pull topology for both the high-side and the low-side drivers.
The peak currents for the drivers are adjustable; their benefits are described in detail in the Slew Rate/Slope
Control section.
18
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