DRV8305_15 Datasheet, PDF (26/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
www.ti.com
7.3.11.8 MCU Watchdog
An MCU watchdog function may be enabled to ensure that the external controller that is instructing the DRV8305
is active and not in an unknown state.
SPI Watchdog must be enabled by writing a 1 to the WD_EN bit through SPI (default is disabled = 0).
When the SPI watchdog is enabled, an internal timer starts to countdown to an interval set by WD_dly bit.
To reset the watchdog, the address 0x01 (Status register) must be read by the microcontroller within the interval
set by the register WD_dly.
If the timer is allowed to expire without the address 0x01 being read, the WD fault will get enabled.
Response to this fault is as follows:
• A Latched + PWRGD fault occurs on the DRV8305 and gate drivers are put into a safe state. The appropriate
recovery sequence must be performed.
• PWRGD pin is taken low for 64 µs and then back high in order to reset the microcontroller.
• nFAULT is asserted
• WD_EN bit is cleared
• Report that the watchdog had expired through SPI bit WD_FAULT
• TI recommends that if the watchdog function is being used, the MCU software routine reads the status
registers as part of its recovery or power-up routine in order to know whether a WD_FAULT had previously
occurred.
Note that the fault results in clearing of the WD_EN bit and it will have to be set again to resume watchdog
functionality.
7.3.12 Pin Control Functions
7.3.12.1 EN_GATE
EN_GATE low is used to put the gate driver into standby mode. Note that EN_GATE has no effect on the LDO
voltage regulator. When EN_GATE is low, the device will always put the MOSFET output stage to high
impedance as long as PVDD is still present. EN_GATE is also used to reset the IC.
It is not possible to enter SLEEP mode without taking EN_GATE low and entering STANDBY mode first.
TI recommends to take EN_GATE for at least greater than 25 µs when it is asserted low to go into standby
mode.
7.3.12.2 SPI Pins
SDO pin has to be tri-state, so a data bus line can be connected to multiple SPI slave devices. SCS pin is active
low. When SCS is high, SDO is at high-impendence mode.
Ensure that SDO pin is always configured in the system as an output from DRV8305.
SDO pin must never be driven to ensure correct operation of DRV8305. SDO is referrenced to the VREG
voltage.
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