DRV8305_15 Datasheet, PDF (22/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
www.ti.com
AVDD is the voltage regulator that provides the voltage rail for the internal analog circuit blocks including the
current sense amplifiers. AVDD is derived from the PVDD voltage supply.
Because the allowed operating range of the device permits operation below the nominal value of AVDD, this
regulator operates in two regimes: namely a linear regulating regime and a dropout region. In the dropout region,
the AVDD will simply track the PVDD voltage minus a voltage drop.
If the device is expected to operate within the dropout region, take care while selecting current sense amplifier
components and settings to accommodate this reduced voltage rail.
7.3.9 Voltage Regulator Output for Driving External Loads (VREG)
The DRV8305 integrates an LDO voltage regulator (VREG) that is dedicated for driving external loads like an
MCU directly. The two versions of the device provide different voltages: DRV83053 provides 3.3 V, DRV83055
provides 5.0 V. Because the user can supply microcontroller and other system power from the DRV8305, the
user does not need to add an external regulator IC for system power.
The DRV8305 voltage regulator is standalone, uncommitted, and is not used internally.
The DRV8305 voltage regulator also features a PWRGD pin to protect against brownouts on externally driven
devices. The PWRGD pin is often tied to a reset pin on a microcontroller to ensure that the microcontroller is
always reset when the voltage is outside of its recommended operation area.
When the voltage output of the LDO drops or exceeds the set threshold (programmable).
• The PWRGD pin will go low for a period of 64 µs.
• After the 64-µs period has expired, the LDO voltage will be checked and PWRGD will be held low until the
LDO voltage has recovered.
The voltage regulator also has undervoltage protection implemented for both the input voltage (PVDD) and
output voltage (VREG).
7.3.10 Protection Features
Fault / Warning Classes and Recovery summarizes the protection features, fault responses, and recovery
sequences.
7.3.10.1 Fault and Protection Handling
The DRV8305 handles fault (latched fault) and warnings (unlatched faults) separately. Both latched and
unlatched faults are reported in status registers and can be read through SPI.
• A latched nFAULT pin indicates an error event has occurred that has caused part of the gate driver to shut
down and force outputs to a safe state (external FETs in high impedance).
– A latched fault is indicated by the nFAULT pin going low (and staying low) and reporting the details of the
fault in the status registers (0x02 and 0x03). The appropriate recovery sequence must be performed in
order to reset the latched fault. In addition, the register (0x01) contains a single status bit if any latched
faults are detected.
– The nFAULT pin will stay low until the appropriate recovery sequence is performed.
TI recommends to inspect the system and board when a latched nFAULT faults occurs.
• An unlatched warning on nFAULT pin indicates that an event that requires a warning to be communicated has
occurred.
– An unlatched fault is indicated by the nFAULT pin going low for a period of 64 µs, reporting the warning
and then recovering back high for a period of 64 µs before reporting any subsequent errors.
– When a warning has been read by SPI through the warning register (0x01), that same warning will not be
reported through nFAULT again unless that warning or condition passes and then reoccurs.
However, the SPI registers will continue to report the latest status of the condition even after it has been
cleared by the read, that is, if the condition has cleared, then the warning will clear in the SPI registers.
Note that if the microprocessor does not read the warning, then the nFAULT pin will continue to toggle.
– In case another warning or warnings are received during the 64-µs period but after the warning register
has been read, then after the expiration of 64 µs, the nFAULT pin will go high for another 64 µs and then
report those warning or warnings by going low for another 64 µs.
– If a latched fault occurs during a period where nFAULT is low, then the nFAULT pin will stay low.
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