DRV8305_15 Datasheet, PDF (31/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

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7.6 Register Maps
DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
Table 9. Register Map
ADDRESS
0x1
0x2
NAME
Warning & Watch
Dog
OV/VDS Faults
0x3
IC Faults
0x4
Gate drvier VGS
Faults
0x5
HS Gate Driver
Control
0x6
LS Gate Driver
Control
0x7
Gate Drive
Control
0x8
Reserved
0x9
IC Operation
0xA
Shunt Amplifier
Control
0xB
Voltage
Regulator Control
0xC
VDS Sense
Control
D10
FAULT
FETHA_VDS
PVDD_UVLO2
FETHA_VGS
Reserved
Reserved
Reserved
Reserved
FLIP_OTS
DC_CAL_CH3
Reserved
Reserved
D9
Reserved
FETLA_VDS
WD_FAULT
D8
TEMP_FLAG4
FETHB_VDS
OTS
D7
PVDD_UVFL
FETLB_VDS
Reserved
FETLA_VGS
FETHB_VGS
FETLB_VGS
TDRIVEN[1]
TDRIVEN[0]
IDRIVEN_HS[3]
TDRIVEP[1]
TDRIVE[0]
IDRIVEN_LS[3]
COMM_OPTION PWM_MODE[1] PWM_MODE[0]
Reserved
DISABLE
VPVDD_UVLO2
Reserved
DIS_GDRV
FAULT
Reserved
EN_SNS_CLAM
P
DC_CAL_CH2 DC_CAL_CH1 CS_BLANK[1]
VREF_SCALE[1] VREF_SCALE[0]
Reserved
Reserved
Reserved
VDS_LEVEL[4]
D6
PVDD_OVFL
FETHC_VDS
VREG_UV
FETHC_VGS
IDRIVEN_HS[2]
IDRIVEN_LS[2]
DEAD_TIME[2]
Reserved
WD_DLY[1]
CS_BLANK[0]
Reserved
VDS_LEVEL[3]
D5
D4
D3
VDS_STATUS
VCPH_UVFL
TEMP_FLAG1
FETLC_VDS
Reserved
Reserved
AVDD_UVLO VCP_LSD_UVLO
Reserved
FETLC_VGS
Reserved
Reserved
IDRIVEN_HS[1] IDRIVEN_HS[0] IDRIVEP_HS[3]
IDRIVEN_LS[1] IDRIVEN_LS[0] IDRIVEP_LS[3]
DEAD_TIME[1]
Reserved
WD_DLY[0]
DEAD_TIME[0]
Reserved
DIS_SNS_OCP
TBLANK[1]
Reserved
WD_EN
GAIN_CS3[1]
GAIN_CS3[0]
GAIN_CS2[1]
Reserved
SLEEP_DLY[1] SLEEP_DLY[0]
VDS_LEVEL[2] VDS_LEVEL[1] VDS_LEVEL[0]
D2
TEMP_FLAG2
SNS_C_OCP
VCPH_UVLO
Reserved
D1
TEMP_FLAG3
SNS_B_OCP
VCPH_OVLO
Reserved
D0
OTW
SNS_A_OCP
VCPH_OVLO_A
BS
Reserved
IDRIVEP_HS[2] IDRIVEP_HS[1] IDRIVEP_HS[0]
IDRIVEP_LS[2] IDRIVEP_LS[1] IDRIVEP_LS[0]
TBLANK[0]
Reserved
SLEEP
TVDS[1]
Reserved
CLR_FLTS
TVDS[0]
Reserved
SET_VCPH_UV
GAIN_CS2[0]
GAIN_CS1[1]
GAIN_CS1[0]
DIS_VREG_PW VREG_UV_LEVE VREG_UV_LEVE
RGD
L[1]
L[0]
VDS_MODE[2] VDS_MODE[1] VDS_MODE[0]
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